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| 111 | * US3 processors have a write-invalidate cache, so explicitly |
111 | * US3 processors have a write-invalidate cache, so explicitly |
| 112 | * invalidating it is not required. Whether to invalidate I-cache |
112 | * invalidating it is not required. Whether to invalidate I-cache |
| 113 | * or not is decided according to the value of the ver.impl bits |
113 | * or not is decided according to the value of the ver.impl bits |
| 114 | * in the Version register. |
114 | * in the Version register. |
| 115 | */ |
115 | */ |
| 116 | sethi 0x40000, %g0 |
- | |
| 117 | ! the lowest/greatest value of ver.impl for US3 |
116 | ! the lowest/greatest value of ver.impl for US3 |
| 118 | #define FIRST_US3_CPU 0x14 |
117 | #define FIRST_US3_CPU 0x14 |
| 119 | #define LAST_US3_CPU 0x19 |
118 | #define LAST_US3_CPU 0x19 |
| 120 | rdpr %ver, %g2 ! autodetect CPU using the Version register |
119 | rdpr %ver, %g2 ! autodetect CPU using the Version register |
| 121 | sllx %g2, 16, %g2 ! extract ver.impl bits |
120 | sllx %g2, 16, %g2 ! extract ver.impl bits |