WebSVN – HelenOS – Diff – /branches/rcu/kernel/arch/ia32/src/smp/apic.c

 /*
  * Copyright (c) 2001-2004 Jakub Jermar
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  *
  * - Redistributions of source code must retain the above copyright
  *   notice, this list of conditions and the following disclaimer.
  * - Redistributions in binary form must reproduce the above copyright
  *   notice, this list of conditions and the following disclaimer in the
  *   documentation and/or other materials provided with the distribution.
  * - The name of the author may not be used to endorse or promote products
  *   derived from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /** @addtogroup ia32
  * @{
  */
 /** @file
  */
 #include <arch/types.h>
 #include <arch/smp/apic.h>
 #include <arch/smp/ap.h>
 #include <arch/smp/mps.h>
 #include <arch/boot/boot.h>
 #include <mm/page.h>
 #include <time/delay.h>
 #include <interrupt.h>
 #include <arch/interrupt.h>
 #include <print.h>
 #include <arch/asm.h>
 #include <arch.h>
 #include <ddi/irq.h>
 #include <ddi/device.h>
 #ifdef CONFIG_SMP
 /*
  * Advanced Programmable Interrupt Controller for SMP systems.
  * Tested on:
  *  Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
  *  Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
  *  VMware Workstation 5.5 with 2 CPUs
  *  QEMU 0.8.0 with 2-15 CPUs
  *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
  *  ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
  *  MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
  */
 /*
  * These variables either stay configured as initilalized, or are changed by
  * the MP configuration code.
  *
  * Pay special attention to the volatile keyword. Without it, gcc -O2 would
  * optimize the code too much and accesses to l_apic and io_apic, that must
  * always be 32-bit, would use byte oriented instructions.
  */
 volatile uint32_t *l_apic = (uint32_t *) 0xfee00000;
 volatile uint32_t *io_apic = (uint32_t *) 0xfec00000;
 uint32_t apic_id_mask = 0;
 static irq_t l_apic_timer_irq;
 static int apic_poll_errors(void);
 #ifdef LAPIC_VERBOSE
 static char *delmod_str[] = {
     "Fixed",
     "Lowest Priority",
     "SMI",
     "Reserved",
     "NMI",
     "INIT",
     "STARTUP",
     "ExtInt"
 };
 static char *destmod_str[] = {
     "Physical",
     "Logical"
 };
 static char *trigmod_str[] = {
     "Edge",
     "Level"
 };
 static char *mask_str[] = {
     "Unmasked",
     "Masked"
 };
 static char *delivs_str[] = {
     "Idle",
     "Send Pending"
 };
 static char *tm_mode_str[] = {
     "One-shot",
     "Periodic"
 };
 static char *intpol_str[] = {
     "Polarity High",
     "Polarity Low"
 };
 #endif /* LAPIC_VERBOSE */
 /** APIC spurious interrupt handler.
  *
  * @param n Interrupt vector.
  * @param istate Interrupted state.
  */
 static void apic_spurious(int n, istate_t *istate)
 {
 #ifdef CONFIG_DEBUG
     printf("cpu%d: APIC spurious interrupt\n", CPU->id);
 #endif
 }
 static irq_ownership_t l_apic_timer_claim(void)
 {
     return IRQ_ACCEPT;
 }
 static void l_apic_timer_irq_handler(irq_t *irq, void *arg, ...)
 {
-    clock();
+    /*
-}
+     * Holding a spinlock could prevent clock() from preempting
+     * the current thread. In this case, we don't need to hold the
-/** Initialize APIC on BSP. */
+     * irq->lock so we just unlock it and then lock it again.
-void apic_init(void)
+     */
-{
+    spinlock_unlock(&irq->lock);
-    io_apic_id_t idreg;
+    clock();
-    unsigned int i;
+    spinlock_lock(&irq->lock);
+}
-    exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
+/** Initialize APIC on BSP. */
-    enable_irqs_function = io_apic_enable_irqs;
+void apic_init(void)
-    disable_irqs_function = io_apic_disable_irqs;
+{
-    eoi_function = l_apic_eoi;
+    io_apic_id_t idreg;
+    unsigned int i;
-    /*
-     * Configure interrupt routing.
+    exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
-     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
-     * Other interrupts will be forwarded to the lowest priority CPU.
+    enable_irqs_function = io_apic_enable_irqs;
-     */
+    disable_irqs_function = io_apic_disable_irqs;
-    io_apic_disable_irqs(0xffff);
+    eoi_function = l_apic_eoi;
-    irq_initialize(&l_apic_timer_irq);
+    /*
-    l_apic_timer_irq.devno = device_assign_devno();
+     * Configure interrupt routing.
-    l_apic_timer_irq.inr = IRQ_CLK;
+     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
-    l_apic_timer_irq.claim = l_apic_timer_claim;
+     * Other interrupts will be forwarded to the lowest priority CPU.
-    l_apic_timer_irq.handler = l_apic_timer_irq_handler;
+     */
-    irq_register(&l_apic_timer_irq);
+    io_apic_disable_irqs(0xffff);
-    for (i = 0; i < IRQ_COUNT; i++) {
+    irq_initialize(&l_apic_timer_irq);
-        int pin;
+    l_apic_timer_irq.preack = true;
+    l_apic_timer_irq.devno = device_assign_devno();
-        if ((pin = smp_irq_to_pin(i)) != -1)
+    l_apic_timer_irq.inr = IRQ_CLK;
-            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI);
+    l_apic_timer_irq.claim = l_apic_timer_claim;
-    }
+    l_apic_timer_irq.handler = l_apic_timer_irq_handler;
+    irq_register(&l_apic_timer_irq);
-    /*
-     * Ensure that io_apic has unique ID.
+    for (i = 0; i < IRQ_COUNT; i++) {
-     */
+        int pin;
-    idreg.value = io_apic_read(IOAPICID);
-    if ((1 << idreg.apic_id) & apic_id_mask) {  /* see if IO APIC ID is used already */
+        if ((pin = smp_irq_to_pin(i)) != -1)
-        for (i = 0; i < APIC_ID_COUNT; i++) {
+            io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE + i, LOPRI);
-            if (!((1 << i) & apic_id_mask)) {
+    }
-                idreg.apic_id = i;
-                io_apic_write(IOAPICID, idreg.value);
+    /*
-                break;
+     * Ensure that io_apic has unique ID.
-            }
+     */
-        }
+    idreg.value = io_apic_read(IOAPICID);
-    }
+    if ((1 << idreg.apic_id) & apic_id_mask) {  /* see if IO APIC ID is used already */
+        for (i = 0; i < APIC_ID_COUNT; i++) {
-    /*
+            if (!((1 << i) & apic_id_mask)) {
-     * Configure the BSP's lapic.
+                idreg.apic_id = i;
-     */
+                io_apic_write(IOAPICID, idreg.value);
-    l_apic_init();
+                break;
+            }
-    l_apic_debug();
+        }
-}
+    }
-/** Poll for APIC errors.
+    /*
- *
+     * Configure the BSP's lapic.
- * Examine Error Status Register and report all errors found.
+     */
- *
+    l_apic_init();
- * @return 0 on error, 1 on success.
- */
+    l_apic_debug();
-int apic_poll_errors(void)
+}
-{
-    esr_t esr;
+/** Poll for APIC errors.
+ *
-    esr.value = l_apic[ESR];
+ * Examine Error Status Register and report all errors found.
+ *
-    if (esr.send_checksum_error)
+ * @return 0 on error, 1 on success.
-        printf("Send Checksum Error\n");
+ */
-    if (esr.receive_checksum_error)
+int apic_poll_errors(void)
-        printf("Receive Checksum Error\n");
+{
-    if (esr.send_accept_error)
+    esr_t esr;
-        printf("Send Accept Error\n");
-    if (esr.receive_accept_error)
+    esr.value = l_apic[ESR];
-        printf("Receive Accept Error\n");
-    if (esr.send_illegal_vector)
+    if (esr.send_checksum_error)
-        printf("Send Illegal Vector\n");
+        printf("Send Checksum Error\n");
-    if (esr.received_illegal_vector)
+    if (esr.receive_checksum_error)
-        printf("Received Illegal Vector\n");
+        printf("Receive Checksum Error\n");
-    if (esr.illegal_register_address)
+    if (esr.send_accept_error)
-        printf("Illegal Register Address\n");
+        printf("Send Accept Error\n");
+    if (esr.receive_accept_error)
-    return !esr.err_bitmap;
+        printf("Receive Accept Error\n");
-}
+    if (esr.send_illegal_vector)
+        printf("Send Illegal Vector\n");
-/** Send all CPUs excluding CPU IPI vector.
+    if (esr.received_illegal_vector)
- *
+        printf("Received Illegal Vector\n");
- * @param vector Interrupt vector to be sent.
+    if (esr.illegal_register_address)
- *
+        printf("Illegal Register Address\n");
- * @return 0 on failure, 1 on success.
- */
+    return !esr.err_bitmap;
-int l_apic_broadcast_custom_ipi(uint8_t vector)
+}
-{
-    icr_t icr;
+/** Send all CPUs excluding CPU IPI vector.
+ *
-    icr.lo = l_apic[ICRlo];
+ * @param vector Interrupt vector to be sent.
-    icr.delmod = DELMOD_FIXED;
+ *
-    icr.destmod = DESTMOD_LOGIC;
+ * @return 0 on failure, 1 on success.
-    icr.level = LEVEL_ASSERT;
+ */
-    icr.shorthand = SHORTHAND_ALL_EXCL;
+int l_apic_broadcast_custom_ipi(uint8_t vector)
-    icr.trigger_mode = TRIGMOD_LEVEL;
+{
-    icr.vector = vector;
+    icr_t icr;
-    l_apic[ICRlo] = icr.lo;
+    icr.lo = l_apic[ICRlo];
+    icr.delmod = DELMOD_FIXED;
-    icr.lo = l_apic[ICRlo];
+    icr.destmod = DESTMOD_LOGIC;
-    if (icr.delivs == DELIVS_PENDING) {
+    icr.level = LEVEL_ASSERT;
-#ifdef CONFIG_DEBUG
+    icr.shorthand = SHORTHAND_ALL_EXCL;
-        printf("IPI is pending.\n");
+    icr.trigger_mode = TRIGMOD_LEVEL;
-#endif
+    icr.vector = vector;
-    }
+    l_apic[ICRlo] = icr.lo;
-    return apic_poll_errors();
-}
+    icr.lo = l_apic[ICRlo];
+    if (icr.delivs == DELIVS_PENDING) {
-/** Universal Start-up Algorithm for bringing up the AP processors.
+#ifdef CONFIG_DEBUG
- *
+        printf("IPI is pending.\n");
- * @param apicid APIC ID of the processor to be brought up.
+#endif
- *
+    }
- * @return 0 on failure, 1 on success.
- */
+    return apic_poll_errors();
-int l_apic_send_init_ipi(uint8_t apicid)
+}
-{
-    icr_t icr;
+/** Universal Start-up Algorithm for bringing up the AP processors.
-    int i;
+ *
+ * @param apicid APIC ID of the processor to be brought up.
-    /*
+ *
-     * Read the ICR register in and zero all non-reserved fields.
+ * @return 0 on failure, 1 on success.
-     */
+ */
-    icr.lo = l_apic[ICRlo];
+int l_apic_send_init_ipi(uint8_t apicid)
-    icr.hi = l_apic[ICRhi];
+{
+    icr_t icr;
-    icr.delmod = DELMOD_INIT;
+    int i;
-    icr.destmod = DESTMOD_PHYS;
-    icr.level = LEVEL_ASSERT;
+    /*
-    icr.trigger_mode = TRIGMOD_LEVEL;
+     * Read the ICR register in and zero all non-reserved fields.
-    icr.shorthand = SHORTHAND_NONE;
+     */
-    icr.vector = 0;
+    icr.lo = l_apic[ICRlo];
-    icr.dest = apicid;
+    icr.hi = l_apic[ICRhi];
-    l_apic[ICRhi] = icr.hi;
+    icr.delmod = DELMOD_INIT;
-    l_apic[ICRlo] = icr.lo;
+    icr.destmod = DESTMOD_PHYS;
+    icr.level = LEVEL_ASSERT;
-    /*
+    icr.trigger_mode = TRIGMOD_LEVEL;
-     * According to MP Specification, 20us should be enough to
+    icr.shorthand = SHORTHAND_NONE;
-     * deliver the IPI.
+    icr.vector = 0;
-     */
+    icr.dest = apicid;
-    delay(20);
+    l_apic[ICRhi] = icr.hi;
-    if (!apic_poll_errors())
+    l_apic[ICRlo] = icr.lo;
-        return 0;
+    /*
-    icr.lo = l_apic[ICRlo];
+     * According to MP Specification, 20us should be enough to
-    if (icr.delivs == DELIVS_PENDING) {
+     * deliver the IPI.
-#ifdef CONFIG_DEBUG
+     */
-        printf("IPI is pending.\n");
+    delay(20);
-#endif
-    }
+    if (!apic_poll_errors())
+        return 0;
-    icr.delmod = DELMOD_INIT;
-    icr.destmod = DESTMOD_PHYS;
+    icr.lo = l_apic[ICRlo];
-    icr.level = LEVEL_DEASSERT;
+    if (icr.delivs == DELIVS_PENDING) {
-    icr.shorthand = SHORTHAND_NONE;
+#ifdef CONFIG_DEBUG
-    icr.trigger_mode = TRIGMOD_LEVEL;
+        printf("IPI is pending.\n");
-    icr.vector = 0;
+#endif
-    l_apic[ICRlo] = icr.lo;
+    }
-    /*
+    icr.delmod = DELMOD_INIT;
-     * Wait 10ms as MP Specification specifies.
+    icr.destmod = DESTMOD_PHYS;
-     */
+    icr.level = LEVEL_DEASSERT;
-    delay(10000);
+    icr.shorthand = SHORTHAND_NONE;
+    icr.trigger_mode = TRIGMOD_LEVEL;
-    if (!is_82489DX_apic(l_apic[LAVR])) {
+    icr.vector = 0;
-        /*
+    l_apic[ICRlo] = icr.lo;
-         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
-         */
+    /*
-        for (i = 0; i<2; i++) {
+     * Wait 10ms as MP Specification specifies.
-            icr.lo = l_apic[ICRlo];
+     */
-            icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */
+    delay(10000);
-            icr.delmod = DELMOD_STARTUP;
-            icr.destmod = DESTMOD_PHYS;
+    if (!is_82489DX_apic(l_apic[LAVR])) {
-            icr.level = LEVEL_ASSERT;
+        /*
-            icr.shorthand = SHORTHAND_NONE;
+         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
-            icr.trigger_mode = TRIGMOD_LEVEL;
+         */
-            l_apic[ICRlo] = icr.lo;
+        for (i = 0; i<2; i++) {
-            delay(200);
+            icr.lo = l_apic[ICRlo];
-        }
+            icr.vector = ((uintptr_t) ap_boot) / 4096; /* calculate the reset vector */
-    }
+            icr.delmod = DELMOD_STARTUP;
+            icr.destmod = DESTMOD_PHYS;
-    return apic_poll_errors();
+            icr.level = LEVEL_ASSERT;
-}
+            icr.shorthand = SHORTHAND_NONE;
+            icr.trigger_mode = TRIGMOD_LEVEL;
-/** Initialize Local APIC. */
+            l_apic[ICRlo] = icr.lo;
-void l_apic_init(void)
+            delay(200);
-{
+        }
-    lvt_error_t error;
+    }
-    lvt_lint_t lint;
-    tpr_t tpr;
+    return apic_poll_errors();
-    svr_t svr;
+}
-    icr_t icr;
-    tdcr_t tdcr;
+/** Initialize Local APIC. */
-    lvt_tm_t tm;
+void l_apic_init(void)
-    ldr_t ldr;
+{
-    dfr_t dfr;
+    lvt_error_t error;
-    uint32_t t1, t2;
+    lvt_lint_t lint;
+    tpr_t tpr;
-    /* Initialize LVT Error register. */
+    svr_t svr;
-    error.value = l_apic[LVT_Err];
+    icr_t icr;
-    error.masked = true;
+    tdcr_t tdcr;
-    l_apic[LVT_Err] = error.value;
+    lvt_tm_t tm;
+    ldr_t ldr;
-    /* Initialize LVT LINT0 register. */
+    dfr_t dfr;
-    lint.value = l_apic[LVT_LINT0];
+    uint32_t t1, t2;
-    lint.masked = true;
-    l_apic[LVT_LINT0] = lint.value;
+    /* Initialize LVT Error register. */
+    error.value = l_apic[LVT_Err];
-    /* Initialize LVT LINT1 register. */
+    error.masked = true;
-    lint.value = l_apic[LVT_LINT1];
+    l_apic[LVT_Err] = error.value;
-    lint.masked = true;
-    l_apic[LVT_LINT1] = lint.value;
+    /* Initialize LVT LINT0 register. */
+    lint.value = l_apic[LVT_LINT0];
-    /* Task Priority Register initialization. */
+    lint.masked = true;
-    tpr.value = l_apic[TPR];
+    l_apic[LVT_LINT0] = lint.value;
-    tpr.pri_sc = 0;
-    tpr.pri = 0;
+    /* Initialize LVT LINT1 register. */
-    l_apic[TPR] = tpr.value;
+    lint.value = l_apic[LVT_LINT1];
+    lint.masked = true;
-    /* Spurious-Interrupt Vector Register initialization. */
+    l_apic[LVT_LINT1] = lint.value;
-    svr.value = l_apic[SVR];
-    svr.vector = VECTOR_APIC_SPUR;
+    /* Task Priority Register initialization. */
-    svr.lapic_enabled = true;
+    tpr.value = l_apic[TPR];
-    svr.focus_checking = true;
+    tpr.pri_sc = 0;
-    l_apic[SVR] = svr.value;
+    tpr.pri = 0;
+    l_apic[TPR] = tpr.value;
-    if (CPU->arch.family >= 6)
-        enable_l_apic_in_msr();
+    /* Spurious-Interrupt Vector Register initialization. */
+    svr.value = l_apic[SVR];
-    /* Interrupt Command Register initialization. */
+    svr.vector = VECTOR_APIC_SPUR;
-    icr.lo = l_apic[ICRlo];
+    svr.lapic_enabled = true;
-    icr.delmod = DELMOD_INIT;
+    svr.focus_checking = true;
-    icr.destmod = DESTMOD_PHYS;
+    l_apic[SVR] = svr.value;
-    icr.level = LEVEL_DEASSERT;
-    icr.shorthand = SHORTHAND_ALL_INCL;
+    if (CPU->arch.family >= 6)
-    icr.trigger_mode = TRIGMOD_LEVEL;
+        enable_l_apic_in_msr();
-    l_apic[ICRlo] = icr.lo;
+    /* Interrupt Command Register initialization. */
-    /* Timer Divide Configuration Register initialization. */
+    icr.lo = l_apic[ICRlo];
-    tdcr.value = l_apic[TDCR];
+    icr.delmod = DELMOD_INIT;
-    tdcr.div_value = DIVIDE_1;
+    icr.destmod = DESTMOD_PHYS;
-    l_apic[TDCR] = tdcr.value;
+    icr.level = LEVEL_DEASSERT;
+    icr.shorthand = SHORTHAND_ALL_INCL;
-    /* Program local timer. */
+    icr.trigger_mode = TRIGMOD_LEVEL;
-    tm.value = l_apic[LVT_Tm];
+    l_apic[ICRlo] = icr.lo;
-    tm.vector = VECTOR_CLK;
-    tm.mode = TIMER_PERIODIC;
+    /* Timer Divide Configuration Register initialization. */
-    tm.masked = false;
+    tdcr.value = l_apic[TDCR];
-    l_apic[LVT_Tm] = tm.value;
+    tdcr.div_value = DIVIDE_1;
+    l_apic[TDCR] = tdcr.value;
-    /*
-     * Measure and configure the timer to generate timer
+    /* Program local timer. */
-     * interrupt with period 1s/HZ seconds.
+    tm.value = l_apic[LVT_Tm];
-     */
+    tm.vector = VECTOR_CLK;
-    t1 = l_apic[CCRT];
+    tm.mode = TIMER_PERIODIC;
-    l_apic[ICRT] = 0xffffffff;
+    tm.masked = false;
+    l_apic[LVT_Tm] = tm.value;
-    while (l_apic[CCRT] == t1)
-        ;
+    /*
+     * Measure and configure the timer to generate timer
-    t1 = l_apic[CCRT];
+     * interrupt with period 1s/HZ seconds.
-    delay(1000000/HZ);
+     */
-    t2 = l_apic[CCRT];
+    t1 = l_apic[CCRT];
+    l_apic[ICRT] = 0xffffffff;
-    l_apic[ICRT] = t1-t2;
+    while (l_apic[CCRT] == t1)
-    /* Program Logical Destination Register. */
+        ;
-    ldr.value = l_apic[LDR];
-    if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
+    t1 = l_apic[CCRT];
-        ldr.id = (1<<CPU->id);
+    delay(1000000/HZ);
-    l_apic[LDR] = ldr.value;
+    t2 = l_apic[CCRT];
-    /* Program Destination Format Register for Flat mode. */
+    l_apic[ICRT] = t1-t2;
-    dfr.value = l_apic[DFR];
-    dfr.model = MODEL_FLAT;
+    /* Program Logical Destination Register. */
-    l_apic[DFR] = dfr.value;
+    ldr.value = l_apic[LDR];
-}
+    if (CPU->id < sizeof(CPU->id)*8)    /* size in bits */
+        ldr.id = (1<<CPU->id);
-/** Local APIC End of Interrupt. */
+    l_apic[LDR] = ldr.value;
-void l_apic_eoi(void)
-{
+    /* Program Destination Format Register for Flat mode. */
-    l_apic[EOI] = 0;
+    dfr.value = l_apic[DFR];
-}
+    dfr.model = MODEL_FLAT;
+    l_apic[DFR] = dfr.value;
-/** Dump content of Local APIC registers. */
+}
-void l_apic_debug(void)
-{
+/** Local APIC End of Interrupt. */
-#ifdef LAPIC_VERBOSE
+void l_apic_eoi(void)
-    lvt_tm_t tm;
+{
-    lvt_lint_t lint;
+    l_apic[EOI] = 0;
-    lvt_error_t error;
+}
-    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
+/** Dump content of Local APIC registers. */
+void l_apic_debug(void)
-    tm.value = l_apic[LVT_Tm];
+{
-    printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
+#ifdef LAPIC_VERBOSE
-    lint.value = l_apic[LVT_LINT0];
+    lvt_tm_t tm;
-    printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
+    lvt_lint_t lint;
-    lint.value = l_apic[LVT_LINT1];
+    lvt_error_t error;
-    printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
-    error.value = l_apic[LVT_Err];
+    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
-    printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
-#endif
+    tm.value = l_apic[LVT_Tm];
-}
+    printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
+    lint.value = l_apic[LVT_LINT0];
-/** Get Local APIC ID.
+    printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
- *
+    lint.value = l_apic[LVT_LINT1];
- * @return Local APIC ID.
+    printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
- */
+    error.value = l_apic[LVT_Err];
-uint8_t l_apic_id(void)
+    printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
-{
+#endif
-    l_apic_id_t idreg;
+}
-    idreg.value = l_apic[L_APIC_ID];
+/** Get Local APIC ID.
-    return idreg.apic_id;
+ *
-}
+ * @return Local APIC ID.
+ */
-/** Read from IO APIC register.
+uint8_t l_apic_id(void)
- *
+{
- * @param address IO APIC register address.
+    l_apic_id_t idreg;
- *
- * @return Content of the addressed IO APIC register.
+    idreg.value = l_apic[L_APIC_ID];
- */
+    return idreg.apic_id;
-uint32_t io_apic_read(uint8_t address)
+}
-{
-    io_regsel_t regsel;
+/** Read from IO APIC register.
+ *
-    regsel.value = io_apic[IOREGSEL];
+ * @param address IO APIC register address.
-    regsel.reg_addr = address;
+ *
-    io_apic[IOREGSEL] = regsel.value;
+ * @return Content of the addressed IO APIC register.
-    return io_apic[IOWIN];
+ */
-}
+uint32_t io_apic_read(uint8_t address)
+{
-/** Write to IO APIC register.
+    io_regsel_t regsel;
- *
- * @param address IO APIC register address.
+    regsel.value = io_apic[IOREGSEL];
- * @param x Content to be written to the addressed IO APIC register.
+    regsel.reg_addr = address;
- */
+    io_apic[IOREGSEL] = regsel.value;
-void io_apic_write(uint8_t address, uint32_t x)
+    return io_apic[IOWIN];
-{
+}
-    io_regsel_t regsel;
+/** Write to IO APIC register.
-    regsel.value = io_apic[IOREGSEL];
+ *
-    regsel.reg_addr = address;
+ * @param address IO APIC register address.
-    io_apic[IOREGSEL] = regsel.value;
+ * @param x Content to be written to the addressed IO APIC register.
-    io_apic[IOWIN] = x;
+ */
-}
+void io_apic_write(uint8_t address, uint32_t x)
+{
-/** Change some attributes of one item in I/O Redirection Table.
+    io_regsel_t regsel;
- *
- * @param pin IO APIC pin number.
+    regsel.value = io_apic[IOREGSEL];
- * @param dest Interrupt destination address.
+    regsel.reg_addr = address;
- * @param v Interrupt vector to trigger.
+    io_apic[IOREGSEL] = regsel.value;
- * @param flags Flags.
+    io_apic[IOWIN] = x;
- */
+}
-void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags)
-{
+/** Change some attributes of one item in I/O Redirection Table.
-    io_redirection_reg_t reg;
+ *
-    int dlvr = DELMOD_FIXED;
+ * @param pin IO APIC pin number.
+ * @param dest Interrupt destination address.
-    if (flags & LOPRI)
+ * @param v Interrupt vector to trigger.
-        dlvr = DELMOD_LOWPRI;
+ * @param flags Flags.
+ */
-    reg.lo = io_apic_read(IOREDTBL + pin*2);
+void io_apic_change_ioredtbl(int pin, int dest, uint8_t v, int flags)
-    reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
+{
+    io_redirection_reg_t reg;
-    reg.dest = dest;
+    int dlvr = DELMOD_FIXED;
-    reg.destmod = DESTMOD_LOGIC;
-    reg.trigger_mode = TRIGMOD_EDGE;
+    if (flags & LOPRI)
-    reg.intpol = POLARITY_HIGH;
+        dlvr = DELMOD_LOWPRI;
-    reg.delmod = dlvr;
-    reg.intvec = v;
+    reg.lo = io_apic_read(IOREDTBL + pin*2);
+    reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
-    io_apic_write(IOREDTBL + pin*2, reg.lo);
-    io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
+    reg.dest = dest;
-}
+    reg.destmod = DESTMOD_LOGIC;
+    reg.trigger_mode = TRIGMOD_EDGE;
-/** Mask IRQs in IO APIC.
+    reg.intpol = POLARITY_HIGH;
- *
+    reg.delmod = dlvr;
- * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
+    reg.intvec = v;
- */
-void io_apic_disable_irqs(uint16_t irqmask)
+    io_apic_write(IOREDTBL + pin*2, reg.lo);
-{
+    io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
-    io_redirection_reg_t reg;
+}
-    unsigned int i;
-    int pin;
+/** Mask IRQs in IO APIC.
+ *
-    for (i = 0; i < 16; i++) {
+ * @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
-        if (irqmask & (1 << i)) {
+ */
-            /*
+void io_apic_disable_irqs(uint16_t irqmask)
-             * Mask the signal input in IO APIC if there is a
+{
-             * mapping for the respective IRQ number.
+    io_redirection_reg_t reg;
-             */
+    unsigned int i;
-            pin = smp_irq_to_pin(i);
+    int pin;
-            if (pin != -1) {
-                reg.lo = io_apic_read(IOREDTBL + pin * 2);
+    for (i = 0; i < 16; i++) {
-                reg.masked = true;
+        if (irqmask & (1 << i)) {
-                io_apic_write(IOREDTBL + pin * 2, reg.lo);
+            /*
-            }
+             * Mask the signal input in IO APIC if there is a
+             * mapping for the respective IRQ number.
-        }
+             */
-    }
+            pin = smp_irq_to_pin(i);
-}
+            if (pin != -1) {
+                reg.lo = io_apic_read(IOREDTBL + pin * 2);
-/** Unmask IRQs in IO APIC.
+                reg.masked = true;
- *
+                io_apic_write(IOREDTBL + pin * 2, reg.lo);
- * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
+            }
- */
-void io_apic_enable_irqs(uint16_t irqmask)
+        }
-{
+    }
-    unsigned int i;
+}
-    int pin;
-    io_redirection_reg_t reg;
+/** Unmask IRQs in IO APIC.
+ *
-    for (i = 0;i < 16; i++) {
+ * @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
-        if (irqmask & (1 << i)) {
+ */
-            /*
+void io_apic_enable_irqs(uint16_t irqmask)
-             * Unmask the signal input in IO APIC if there is a
+{
-             * mapping for the respective IRQ number.
+    unsigned int i;
-             */
+    int pin;
-            pin = smp_irq_to_pin(i);
+    io_redirection_reg_t reg;
-            if (pin != -1) {
-                reg.lo = io_apic_read(IOREDTBL + pin * 2);
+    for (i = 0;i < 16; i++) {
-                reg.masked = false;
+        if (irqmask & (1 << i)) {
-                io_apic_write(IOREDTBL + pin * 2, reg.lo);
+            /*
-            }
+             * Unmask the signal input in IO APIC if there is a
+             * mapping for the respective IRQ number.
-        }
+             */
-    }
+            pin = smp_irq_to_pin(i);
-}
+            if (pin != -1) {
+                reg.lo = io_apic_read(IOREDTBL + pin * 2);
-#endif /* CONFIG_SMP */
+                reg.masked = false;
+                io_apic_write(IOREDTBL + pin * 2, reg.lo);
-/** @}
+            }
- */
+        }
+    }
+}
+#endif /* CONFIG_SMP */
+/** @}
+ */

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(root)/branches/rcu/kernel/arch/ia32/src/smp/apic.c – Rev 2131 → 2265