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#include <ddi/irq.h>
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#include <ddi/irq.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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#include <mm/slab.h>
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#include <mm/slab.h>
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#include <ddi/device.h>
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#include <ddi/device.h>
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static indev_operations_t kbrdin_ops = {
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    .poll = NULL
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};
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static inline void z8530_write(ioport8_t *ctl, uint8_t reg, uint8_t val)
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static inline void z8530_write(ioport8_t *ctl, uint8_t reg, uint8_t val)
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{
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{
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    /*
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    /*
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     * Registers 8-15 will automatically issue the Point High
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     * Registers 8-15 will automatically issue the Point High
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     * command as their bit 3 is 1.
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     * command as their bit 3 is 1.
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{
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{
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    z8530_instance_t *instance = irq->instance;
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    z8530_instance_t *instance = irq->instance;
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    z8530_t *dev = instance->z8530;
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    z8530_t *dev = instance->z8530;
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    if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) {
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    if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) {
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        uint8_t x = z8530_read(&dev->ctl_a, RR8);
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        uint8_t data = z8530_read(&dev->ctl_a, RR8);
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        indev_push_character(&instance->kbrdin, x);
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        indev_push_character(instance->kbrdin, data);
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    }
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    }
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}
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}
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/** Initialize z8530. */
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/** Initialize z8530. */
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indev_t *z8530_init(z8530_t *dev, inr_t inr, cir_t cir, void *cir_arg)
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z8530_instance_t *z8530_init(z8530_t *dev, inr_t inr, cir_t cir, void *cir_arg)
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{
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{
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    z8530_instance_t *instance
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    z8530_instance_t *instance
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        = malloc(sizeof(z8530_instance_t), FRAME_ATOMIC);
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        = malloc(sizeof(z8530_instance_t), FRAME_ATOMIC);
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    if (!instance)
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    if (instance) {
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        instance->z8530 = dev;
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        instance->kbrdin = NULL;
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        irq_initialize(&instance->irq);
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        instance->irq.devno = device_assign_devno();
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        return false;
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        instance->irq.inr = inr;
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        instance->irq.claim = z8530_claim;
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        instance->irq.handler = z8530_irq_handler;
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        instance->irq.instance = instance;
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        instance->irq.cir = cir;
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        instance->irq.cir_arg = cir_arg;
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    }
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    return instance;
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}
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    indev_initialize("z8530", &instance->kbrdin, &kbrdin_ops);
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void z8530_wire(z8530_instance_t *instance, indev_t *kbrdin)
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{
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    ASSERT(instance);
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    ASSERT(kbrdin);
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    instance->z8530 = dev;
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    instance->kbrdin = kbrdin;
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    irq_initialize(&instance->irq);
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    instance->irq.devno = device_assign_devno();
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    instance->irq.inr = inr;
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    instance->irq.claim = z8530_claim;
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    instance->irq.handler = z8530_irq_handler;
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    instance->irq.instance = instance;
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    instance->irq.cir = cir;
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    instance->irq.cir_arg = cir_arg;
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    irq_register(&instance->irq);
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    irq_register(&instance->irq);
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    (void) z8530_read(&dev->ctl_a, RR8);
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    (void) z8530_read(&instance->z8530->ctl_a, RR8);
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    /*
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    /*
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     * Clear any pending TX interrupts or we never manage
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     * Clear any pending TX interrupts or we never manage
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     * to set FHC UART interrupt state to idle.
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     * to set FHC UART interrupt state to idle.
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     */
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     */
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    z8530_write(&dev->ctl_a, WR0, WR0_TX_IP_RST);
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    z8530_write(&instance->z8530->ctl_a, WR0, WR0_TX_IP_RST);
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    /* interrupt on all characters */
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    /* interrupt on all characters */
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    z8530_write(&dev->ctl_a, WR1, WR1_IARCSC);
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    z8530_write(&instance->z8530->ctl_a, WR1, WR1_IARCSC);
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    /* 8 bits per character and enable receiver */
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    /* 8 bits per character and enable receiver */
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    z8530_write(&dev->ctl_a, WR3, WR3_RX8BITSCH | WR3_RX_ENABLE);
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    z8530_write(&instance->z8530->ctl_a, WR3, WR3_RX8BITSCH | WR3_RX_ENABLE);
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    /* Master Interrupt Enable. */
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    /* Master Interrupt Enable. */
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    z8530_write(&dev->ctl_a, WR9, WR9_MIE);
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    z8530_write(&instance->z8530->ctl_a, WR9, WR9_MIE);
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    return &instance->kbrdin;
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}
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}
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/** @}
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/** @}
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 */
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 */