WebSVN – HelenOS – Diff – /branches/network/kernel/arch/ia64/src/mm/tlb.c



{
    tlb_invalidate_all();
}
 
 
void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
{
    region_register rr;
    bool restore_rr = false;
    int b = 0;
    int c = cnt;

 * @param entry     The rest of TLB entry as required by TLB insertion
 *          format.
 * @param tr        Translation register.
 */
void
itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
{
    tr_mapping_insert(va, asid, entry, false, tr);
}
 
/** Insert data into data translation register.

 * @param entry     The rest of TLB entry as required by TLB insertion
 *          format.
 * @param tr        Translation register.
 */
void
dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
{
    tr_mapping_insert(va, asid, entry, true, tr);
}
 
/** Insert data into instruction or data translation register.

 *          instruction translation register otherwise.
 * @param tr        Translation register.
 */
void
tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
    size_t tr)
{
    region_register rr;
    bool restore_rr = false;
 
    rr.word = rr_read(VA2VRN(va));

 *          translation cache otherwise.
 * @param tr        Translation register if dtr is true, ignored otherwise.
 */
void
dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
    size_t tr)
{
    tlb_entry_t entry;
   
    entry.word[0] = 0;
    entry.word[1] = 0;

 * Purge DTR entries used by the kernel.
 *
 * @param page      Virtual page address including VRN bits.
 * @param width     Width of the purge in bits.
 */
void dtr_purge(uintptr_t page, size_t width)
{
    asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));
}
 
 

Rev 4153	Rev 4581
Line 98...	Line 98...
98	{	98	{
99	tlb_invalidate_all();	99	tlb_invalidate_all();
100	}	100	}
101		101
102		102
103	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)	103	void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
104	{	104	{
105	region_register rr;	105	region_register rr;
106	bool restore_rr = false;	106	bool restore_rr = false;
107	int b = 0;	107	int b = 0;
108	int c = cnt;	108	int c = cnt;
Line 265...	Line 265...
265	* @param entry The rest of TLB entry as required by TLB insertion	265	* @param entry The rest of TLB entry as required by TLB insertion
266	* format.	266	* format.
267	* @param tr Translation register.	267	* @param tr Translation register.
268	*/	268	*/
269	void	269	void
270	itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)	270	itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
271	{	271	{
272	tr_mapping_insert(va, asid, entry, false, tr);	272	tr_mapping_insert(va, asid, entry, false, tr);
273	}	273	}
274		274
275	/** Insert data into data translation register.	275	/** Insert data into data translation register.
Line 279...	Line 279...
279	* @param entry The rest of TLB entry as required by TLB insertion	279	* @param entry The rest of TLB entry as required by TLB insertion
280	* format.	280	* format.
281	* @param tr Translation register.	281	* @param tr Translation register.
282	*/	282	*/
283	void	283	void
284	dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)	284	dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
285	{	285	{
286	tr_mapping_insert(va, asid, entry, true, tr);	286	tr_mapping_insert(va, asid, entry, true, tr);
287	}	287	}
288		288
289	/** Insert data into instruction or data translation register.	289	/** Insert data into instruction or data translation register.
Line 296...	Line 296...
296	* instruction translation register otherwise.	296	* instruction translation register otherwise.
297	* @param tr Translation register.	297	* @param tr Translation register.
298	*/	298	*/
299	void	299	void
300	tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,	300	tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
301	index_t tr)	301	size_t tr)
302	{	302	{
303	region_register rr;	303	region_register rr;
304	bool restore_rr = false;	304	bool restore_rr = false;
305		305
306	rr.word = rr_read(VA2VRN(va));	306	rr.word = rr_read(VA2VRN(va));
Line 351...	Line 351...
351	* translation cache otherwise.	351	* translation cache otherwise.
352	* @param tr Translation register if dtr is true, ignored otherwise.	352	* @param tr Translation register if dtr is true, ignored otherwise.
353	*/	353	*/
354	void	354	void
355	dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,	355	dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
356	index_t tr)	356	size_t tr)
357	{	357	{
358	tlb_entry_t entry;	358	tlb_entry_t entry;
359		359
360	entry.word[0] = 0;	360	entry.word[0] = 0;
361	entry.word[1] = 0;	361	entry.word[1] = 0;
Line 380...	Line 380...
380	* Purge DTR entries used by the kernel.	380	* Purge DTR entries used by the kernel.
381	*	381	*
382	* @param page Virtual page address including VRN bits.	382	* @param page Virtual page address including VRN bits.
383	* @param width Width of the purge in bits.	383	* @param width Width of the purge in bits.
384	*/	384	*/
385	void dtr_purge(uintptr_t page, count_t width)	385	void dtr_purge(uintptr_t page, size_t width)
386	{	386	{
387	asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));	387	asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));
388	}	388	}
389		389
390		390

Subversion Repositories HelenOS

(root)/branches/network/kernel/arch/ia64/src/mm/tlb.c – Rev 4153 → 4581