WebSVN – HelenOS – Diff – /branches/network/kernel/arch/amd64/include/asm.h

  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 /** @addtogroup amd64
  * @{
  */
 /** @file
  */
 #ifndef KERN_amd64_ASM_H_
 #define KERN_amd64_ASM_H_
 #include <config.h>
+#include <arch/types.h>
+#include <typedefs.h>
 extern void asm_delay_loop(uint32_t t);
 extern void asm_fake_loop(uint32_t t);
 /** Return base address of current stack.
+ *
  * Return the base address of the current stack.
  * The stack is assumed to be STACK_SIZE bytes long.
  * The stack must start on page boundary.
+ *
  */
 static inline uintptr_t get_stack_base(void)
+{
     uintptr_t v;
+    asm volatile (
+        "andq %%rsp, %[v]\n"
+        : [v] "=r" (v)
-    asm volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((uint64_t)STACK_SIZE-1)));
+        : "0" (~((uint64_t) STACK_SIZE-1))
+    );
     return v;
+}
 static inline void cpu_sleep(void)
     asm volatile ("hlt\n");
+}
 static inline void cpu_halt(void)
+{
-    asm volatile ("hlt\n");
+    asm volatile (
+        "0:\n"
+        "   hlt\n"
+        "   jmp 0b\n"
+    );
+}
 /** Byte from port
+ *
  * Get byte from port
+ *
  * @param port Port to read from
  * @return Value read
+ *
  */
-static inline uint8_t inb(uint16_t port)
+static inline uint8_t pio_read_8(ioport8_t *port)
+{
     uint8_t val;
+    asm volatile (
+        "inb %w[port], %b[val]\n"
+        : [val] "=a" (val)
+        : [port] "d" (port)
+    );
+    return val;
+}
+/** Word from port
+ *
+ * Get word from port
+ *
+ * @param port Port to read from
+ * @return Value read
+ *
+ */
-    asm volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port));
+static inline uint16_t pio_read_16(ioport16_t *port)
+{
+    uint16_t val;
+    asm volatile (
+        "inw %w[port], %w[val]\n"
+        : [val] "=a" (val)
+        : [port] "d" (port)
+    );
+    return val;
+}
+/** Double word from port
+ *
+ * Get double word from port
+ *
+ * @param port Port to read from
+ * @return Value read
+ *
+ */
+static inline uint32_t pio_read_32(ioport32_t *port)
+{
+    uint32_t val;
+    asm volatile (
+        "inl %w[port], %[val]\n"
+        : [val] "=a" (val)
+        : [port] "d" (port)
+    );
     return val;
+}
 /** Byte to port
+ *
  * Output byte to port
+ *
  * @param port Port to write to
  * @param val Value to write
+ *
+ */
+static inline void pio_write_8(ioport8_t *port, uint8_t val)
+{
+    asm volatile (
+        "outb %b[val], %w[port]\n"
+        :: [val] "a" (val), [port] "d" (port)
+    );
+}
+/** Word to port
+ *
+ * Output word to port
+ *
+ * @param port Port to write to
+ * @param val Value to write
+ *
  */
-static inline void outb(uint16_t port, uint8_t val)
+static inline void pio_write_16(ioport16_t *port, uint16_t val)
+{
+    asm volatile (
+        "outw %w[val], %w[port]\n"
-    asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port));
+        :: [val] "a" (val), [port] "d" (port)
+    );
+}
+/** Double word to port
+ *
+ * Output double word to port
+ *
+ * @param port Port to write to
+ * @param val Value to write
+ *
+ */
+static inline void pio_write_32(ioport32_t *port, uint32_t val)
+{
+    asm volatile (
+        "outl %[val], %w[port]\n"
+        :: [val] "a" (val), [port] "d" (port)
+    );
+}
 /** Swap Hidden part of GS register with visible one */
 static inline void swapgs(void)
+{
+ *
  * Enable interrupts and return previous
  * value of EFLAGS.
+ *
  * @return Old interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_enable(void) {
     ipl_t v;
-    __asm__ volatile (
+    asm volatile (
         "pushfq\n"
-        "popq %0\n"
+        "popq %[v]\n"
         "sti\n"
-        : "=r" (v)
+        : [v] "=r" (v)
     );
     return v;
+}
 /** Disable interrupts.
+ *
  * Disable interrupts and return previous
  * value of EFLAGS.
+ *
  * @return Old interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_disable(void) {
     ipl_t v;
-    __asm__ volatile (
+    asm volatile (
         "pushfq\n"
-        "popq %0\n"
+        "popq %[v]\n"
         "cli\n"
-        : "=r" (v)
+        : [v] "=r" (v)
-        );
+    );
     return v;
+}
 /** Restore interrupt priority level.
+ *
  * Restore EFLAGS.
+ *
  * @param ipl Saved interrupt priority level.
+ *
  */
 static inline void interrupts_restore(ipl_t ipl) {
-    __asm__ volatile (
+    asm volatile (
-        "pushq %0\n"
+        "pushq %[ipl]\n"
         "popfq\n"
-        : : "r" (ipl)
+        :: [ipl] "r" (ipl)
-        );
+    );
+}
 /** Return interrupt priority level.
+ *
  * Return EFLAFS.
+ *
  * @return Current interrupt priority level.
+ *
  */
 static inline ipl_t interrupts_read(void) {
     ipl_t v;
-    __asm__ volatile (
+    asm volatile (
         "pushfq\n"
-        "popq %0\n"
+        "popq %[v]\n"
-        : "=r" (v)
+        : [v] "=r" (v)
     );
     return v;
+}
 /** Write to MSR */
 static inline void write_msr(uint32_t msr, uint64_t value)
+{
-    __asm__ volatile (
+    asm volatile (
+        "wrmsr\n"
-        "wrmsr;" : : "c" (msr),
+        :: "c" (msr),
-        "a" ((uint32_t)(value)),
+           "a" ((uint32_t) (value)),
-        "d" ((uint32_t)(value >> 32))
+           "d" ((uint32_t) (value >> 32))
-        );
+    );
+}
 static inline unative_t read_msr(uint32_t msr)
+{
     uint32_t ax, dx;
-    __asm__ volatile (
+    asm volatile (
+        "rdmsr\n"
-        "rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
+        : "=a" (ax), "=d" (dx)
+        : "c" (msr)
-        );
+    );
-    return ((uint64_t)dx << 32) | ax;
+    return ((uint64_t) dx << 32) | ax;
+}
 /** Enable local APIC
+ *
  * Enable local APIC in MSR.
+ *
  */
 static inline void enable_l_apic_in_msr()
+{
-    __asm__ volatile (
+    asm volatile (
         "movl $0x1b, %%ecx\n"
         "rdmsr\n"
-        "orl $(1<<11),%%eax\n"
+        "orl $(1 << 11),%%eax\n"
         "orl $(0xfee00000),%%eax\n"
         "wrmsr\n"
-        :
-        :
-        :"%eax","%ecx","%edx"
+        ::: "%eax","%ecx","%edx"
-        );
+    );
+}
 static inline uintptr_t * get_ip()
+{
     uintptr_t *ip;
-    __asm__ volatile (
+    asm volatile (
-        "mov %%rip, %0"
+        "mov %%rip, %[ip]"
-        : "=r" (ip)
+        : [ip] "=r" (ip)
-        );
+    );
     return ip;
+}
 /** Invalidate TLB Entry.
+ *
  * @param addr Address on a page whose TLB entry is to be invalidated.
+ *
  */
 static inline void invlpg(uintptr_t addr)
+{
+    asm volatile (
+        "invlpg %[addr]\n"
-    __asm__ volatile ("invlpg %0\n" :: "m" (*((unative_t *)addr)));
+        :: [addr] "m" (*((unative_t *) addr))
+    );
+}
 /** Load GDTR register from memory.
+ *
  * @param gdtr_reg Address of memory from where to load GDTR.
+ *
  */
-static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
+static inline void gdtr_load(ptr_16_64_t *gdtr_reg)
+{
+    asm volatile (
+        "lgdtq %[gdtr_reg]\n"
-    __asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));
+        :: [gdtr_reg] "m" (*gdtr_reg)
+    );
+}
 /** Store GDTR register to memory.
+ *
  * @param gdtr_reg Address of memory to where to load GDTR.
+ *
  */
-static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
+static inline void gdtr_store(ptr_16_64_t *gdtr_reg)
+{
+    asm volatile (
+        "sgdtq %[gdtr_reg]\n"
-    __asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));
+        :: [gdtr_reg] "m" (*gdtr_reg)
+    );
+}
 /** Load IDTR register from memory.
+ *
  * @param idtr_reg Address of memory from where to load IDTR.
+ *
  */
-static inline void idtr_load(struct ptr_16_64 *idtr_reg)
+static inline void idtr_load(ptr_16_64_t *idtr_reg)
+{
+    asm volatile (
+        "lidtq %[idtr_reg]\n"
-    __asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));
+        :: [idtr_reg] "m" (*idtr_reg));
+}
 /** Load TR from descriptor table.
+ *
  * @param sel Selector specifying descriptor of TSS segment.
+ *
  */
 static inline void tr_load(uint16_t sel)
+{
+    asm volatile (
+        "ltr %[sel]"
-    __asm__ volatile ("ltr %0" : : "r" (sel));
+        :: [sel] "r" (sel)
+    );
+}
 #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \
     { \
-    unative_t res; \
+        unative_t res; \
+        asm volatile ( \
-    __asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
+            "movq %%" #reg ", %[res]" \
+            : [res] "=r" (res) \
+        ); \
-    return res; \
+        return res; \
     }
 #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \
     { \
+        asm volatile ( \
-    __asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
+            "movq %[regn], %%" #reg \
+            :: [regn] "r" (regn) \
-    }
+        ); \
+    }
 GEN_READ_REG(cr0)
 GEN_READ_REG(cr2)
 GEN_READ_REG(cr3)
 GEN_WRITE_REG(cr3)

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(root)/branches/network/kernel/arch/amd64/include/asm.h @ 4326 – Rev 3386 → 4153