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Rev 2927 Rev 3674
Line 43... Line 43...
43 
#include <debug.h>
 43 
#include <debug.h>
44 
#include <print.h>
 44 
#include <print.h>
45 
#include <func.h>
 45 
#include <func.h>
46 
#include <arch/asm.h>
 46 
#include <arch/asm.h>
47 
 
 47 
 
48 
#define PCI_SABRE_REGS_REG  0
 48 
#define SABRE_INTERNAL_REG  0
- 
 
 49 
#define PSYCHO_INTERNAL_REG 2  
49 
 
 50 
 
50 
#define PCI_SABRE_IMAP_BASE 0x200
 51 
#define OBIO_IMR_BASE   0x200
51 
#define PCI_SABRE_ICLR_BASE 0x300
 52 
#define OBIO_IMR(ino)   (OBIO_IMR_BASE + ((ino) & INO_MASK))
52 
 
 53 
 
53 
#define PCI_PSYCHO_REGS_REG 2  
54 
#define OBIO_CIR_BASE   0x300
- 
 
 55 
#define OBIO_CIR(ino)   (OBIO_CIR_BASE + ((ino) & INO_MASK))
54 
 
 56 
 
55 
#define PCI_PSYCHO_IMAP_BASE    0x200
 57 
static void obio_enable_interrupt(pci_t *, int);
56 
#define PCI_PSYCHO_ICLR_BASE    0x300  
58 
static void obio_clear_interrupt(pci_t *, int);
57 
 
 59 
 
58 
static pci_t *pci_sabre_init(ofw_tree_node_t *node);
 60 
static pci_t *pci_sabre_init(ofw_tree_node_t *);
59 
static void pci_sabre_enable_interrupt(pci_t *pci, int inr);
 - 
 
60 
static void pci_sabre_clear_interrupt(pci_t *pci, int inr);
 - 
 
61 
 
 - 
 
62 
static pci_t *pci_psycho_init(ofw_tree_node_t *node);
 61 
static pci_t *pci_psycho_init(ofw_tree_node_t *);
63 
static void pci_psycho_enable_interrupt(pci_t *pci, int inr);
 - 
 
64 
static void pci_psycho_clear_interrupt(pci_t *pci, int inr);
 - 
 
65 
 
 62 
 
66 
/** PCI operations for Sabre model. */
 63 
/** PCI operations for Sabre model. */
67 
static pci_operations_t pci_sabre_ops = {
 64 
static pci_operations_t pci_sabre_ops = {
68 
    .enable_interrupt = pci_sabre_enable_interrupt,
 65 
    .enable_interrupt = obio_enable_interrupt,
69 
    .clear_interrupt = pci_sabre_clear_interrupt
 66 
    .clear_interrupt = obio_clear_interrupt
70 
};
 67 
};
71 
/** PCI operations for Psycho model. */
 68 
/** PCI operations for Psycho model. */
72 
static pci_operations_t pci_psycho_ops = {
 69 
static pci_operations_t pci_psycho_ops = {
73 
    .enable_interrupt = pci_psycho_enable_interrupt,
 70 
    .enable_interrupt = obio_enable_interrupt,
74 
    .clear_interrupt = pci_psycho_clear_interrupt
 71 
    .clear_interrupt = obio_clear_interrupt
75 
};
 72 
};
76 
 
 73 
 
77 
/** Initialize PCI controller (model Sabre).
 74 
/** Initialize PCI controller (model Sabre).
78 
 *
 75 
 *
79 
 * @param node OpenFirmware device tree node of the Sabre.
 76 
 * @param node      OpenFirmware device tree node of the Sabre.
80 
 *
 77 
 *
81 
 * @return Address of the initialized PCI structure.
 78 
 * @return      Address of the initialized PCI structure.
82 
 */
 79 
 */
83 
pci_t *pci_sabre_init(ofw_tree_node_t *node)
 80 
pci_t *pci_sabre_init(ofw_tree_node_t *node)
84 
{
 81 
{
85 
    pci_t *pci;
 82 
    pci_t *pci;
86 
    ofw_tree_property_t *prop;
 83 
    ofw_tree_property_t *prop;
Line 93... Line 90...
93 
        return NULL;
 90 
        return NULL;
94 
 
 91 
 
95 
    ofw_upa_reg_t *reg = prop->value;
 92 
    ofw_upa_reg_t *reg = prop->value;
96 
    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
 93 
    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
97 
 
 94 
 
98 
    if (regs < PCI_SABRE_REGS_REG + 1)
 95 
    if (regs < SABRE_INTERNAL_REG + 1)
99 
        return NULL;
 96 
        return NULL;
100 
 
 97 
 
101 
    uintptr_t paddr;
 98 
    uintptr_t paddr;
102 
    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_SABRE_REGS_REG], &paddr))
 99 
    if (!ofw_upa_apply_ranges(node->parent, &reg[SABRE_INTERNAL_REG],
- 
 
 100 
        &paddr))
103 
        return NULL;
 101 
        return NULL;
104 
 
 102 
 
105 
    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
 103 
    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
106 
    if (!pci)
 104 
    if (!pci)
107 
        return NULL;
 105 
        return NULL;
108 
 
 106 
 
109 
    pci->model = PCI_SABRE;
 107 
    pci->model = PCI_SABRE;
110 
    pci->op = &pci_sabre_ops;
 108 
    pci->op = &pci_sabre_ops;
111 
    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_SABRE_REGS_REG].size);
 109 
    pci->reg = (uint64_t *) hw_map(paddr, reg[SABRE_INTERNAL_REG].size);
112 
 
 110 
 
113 
    return pci;
 111 
    return pci;
114 
}
 112 
}
115 
 
 113 
 
116 
 
 114 
 
117 
/** Initialize the Psycho PCI controller.
 115 
/** Initialize the Psycho PCI controller.
118 
 *
 116 
 *
119 
 * @param node OpenFirmware device tree node of the Psycho.
 117 
 * @param node      OpenFirmware device tree node of the Psycho.
120 
 *
 118 
 *
121 
 * @return Address of the initialized PCI structure.
 119 
 * @return      Address of the initialized PCI structure.
122 
 */
 120 
 */
123 
pci_t *pci_psycho_init(ofw_tree_node_t *node)
 121 
pci_t *pci_psycho_init(ofw_tree_node_t *node)
124 
{
 122 
{
125 
    pci_t *pci;
 123 
    pci_t *pci;
126 
    ofw_tree_property_t *prop;
 124 
    ofw_tree_property_t *prop;
Line 133... Line 131...
133 
        return NULL;
 131 
        return NULL;
134 
 
 132 
 
135 
    ofw_upa_reg_t *reg = prop->value;
 133 
    ofw_upa_reg_t *reg = prop->value;
136 
    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
 134 
    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
137 
 
 135 
 
138 
    if (regs < PCI_PSYCHO_REGS_REG + 1)
 136 
    if (regs < PSYCHO_INTERNAL_REG + 1)
139 
        return NULL;
 137 
        return NULL;
140 
 
 138 
 
141 
    uintptr_t paddr;
 139 
    uintptr_t paddr;
142 
    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_PSYCHO_REGS_REG], &paddr))
 140 
    if (!ofw_upa_apply_ranges(node->parent, &reg[PSYCHO_INTERNAL_REG],
- 
 
 141 
        &paddr))
143 
        return NULL;
 142 
        return NULL;
144 
 
 143 
 
145 
    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
 144 
    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
146 
    if (!pci)
 145 
    if (!pci)
147 
        return NULL;
 146 
        return NULL;
148 
 
 147 
 
149 
    pci->model = PCI_PSYCHO;
 148 
    pci->model = PCI_PSYCHO;
150 
    pci->op = &pci_psycho_ops;
 149 
    pci->op = &pci_psycho_ops;
151 
    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_PSYCHO_REGS_REG].size);
 150 
    pci->reg = (uint64_t *) hw_map(paddr, reg[PSYCHO_INTERNAL_REG].size);
152 
 
 151 
 
153 
    return pci;
 152 
    return pci;
154 
}
 153 
}
155 
 
 154 
 
156 
void pci_sabre_enable_interrupt(pci_t *pci, int inr)
 155 
void obio_enable_interrupt(pci_t *pci, int inr)
157 
{
 - 
 
158 
    pci->reg[PCI_SABRE_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
 - 
 
159 
}
 - 
 
160 
 
 - 
 
161 
void pci_sabre_clear_interrupt(pci_t *pci, int inr)
 - 
 
162 
{
 156 
{
163 
    pci->reg[PCI_SABRE_ICLR_BASE + (inr & INO_MASK)] = 0;
 157 
    pci->reg[OBIO_IMR(inr & INO_MASK)] |= IMAP_V_MASK;
164 
}
 158 
}
165 
 
 159 
 
166 
void pci_psycho_enable_interrupt(pci_t *pci, int inr)
 160 
void obio_clear_interrupt(pci_t *pci, int inr)
167 
{
 161 
{
168 
    pci->reg[PCI_PSYCHO_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
 - 
 
169 
}
 - 
 
170 
 
 - 
 
171 
void pci_psycho_clear_interrupt(pci_t *pci, int inr)
 - 
 
172 
{
 - 
 
173 
    pci->reg[PCI_PSYCHO_ICLR_BASE + (inr & INO_MASK)] = 0;
 162 
    pci->reg[OBIO_CIR(inr & INO_MASK)] = 0; /* set IDLE */
174 
}
 163 
}
175 
 
 164 
 
176 
/** Initialize PCI controller. */
 165 
/** Initialize PCI controller. */
177 
pci_t *pci_init(ofw_tree_node_t *node)
 166 
pci_t *pci_init(ofw_tree_node_t *node)
178 
{
 167 
{
Line 213... Line 202...
213 
    return NULL;
 202 
    return NULL;
214 
}
 203 
}
215 
 
 204 
 
216 
void pci_enable_interrupt(pci_t *pci, int inr)
 205 
void pci_enable_interrupt(pci_t *pci, int inr)
217 
{
 206 
{
218 
    ASSERT(pci->model);
 - 
 
219 
    ASSERT(pci->op && pci->op->enable_interrupt);
 207 
    ASSERT(pci->op && pci->op->enable_interrupt);
220 
    pci->op->enable_interrupt(pci, inr);
 208 
    pci->op->enable_interrupt(pci, inr);
221 
}
 209 
}
222 
 
 210 
 
223 
void pci_clear_interrupt(pci_t *pci, int inr)
 211 
void pci_clear_interrupt(void *pcip, int inr)
224 
{
 212 
{
225 
    ASSERT(pci->model);
 213 
    pci_t *pci = (pci_t *)pcip;
- 
 
 214 
 
226 
    ASSERT(pci->op && pci->op->clear_interrupt);
 215 
    ASSERT(pci->op && pci->op->clear_interrupt);
227 
    pci->op->clear_interrupt(pci, inr);
 216 
    pci->op->clear_interrupt(pci, inr);
228 
}
 217 
}
229 
 
 218 
 
230 
/** @}
 219 
/** @}