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#define memory_barrier() asm volatile ("sync" ::: "memory")
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#define memory_barrier() asm volatile ("sync" ::: "memory")
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#define read_barrier() asm volatile ("sync" ::: "memory")
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#define read_barrier() asm volatile ("sync" ::: "memory")
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#define write_barrier() asm volatile ("eieio" ::: "memory")
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#define write_barrier() asm volatile ("eieio" ::: "memory")
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/*
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 * The IMB sequence used here is valid for all possible cache models
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 * on uniprocessor. SMP might require a different sequence.
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 * See PowerPC Programming Environment for 32-Bit Microprocessors,
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 * chapter 5.1.5.2
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 */
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static inline void smc_coherence(void *addr)
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{
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    asm volatile (
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        "dcbst 0, %0\n"
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        "sync\n"
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        "icbi 0, %0\n"
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        "isync\n"
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        :: "r" (addr)
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    );
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}
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#define COHERENCE_INVAL_MIN 4
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static inline void smc_coherence_block(void *addr, unsigned long len)
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{
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    unsigned long i;
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    for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
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        asm volatile ("dcbst 0, %0\n" :: "r" (addr + i));
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    }
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    asm volatile ("sync");
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    for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
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        asm volatile ("icbi 0, %0\n" :: "r" (addr + i));
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    }
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    asm volatile ("isync");
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}
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#endif
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#endif
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/** @}
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/** @}
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 */
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 */