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Line 47... Line 47...
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 *  @return Value stored in CP15 fault status register (FSR).
 47 
 *  @return Value stored in CP15 fault status register (FSR).
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 */
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 */
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static inline fault_status_t read_fault_status_register(void)
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static inline fault_status_t read_fault_status_register(void)
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{
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{
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    fault_status_union_t fsu;
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    fault_status_union_t fsu;
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    /* fault status is stored in CP15 register 5 */
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    /* fault status is stored in CP15 register 5 */
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    asm volatile (
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    asm volatile (
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        "mrc p15, 0, %0, c5, c0, 0"
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        "mrc p15, 0, %[dummy], c5, c0, 0"
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        : "=r"(fsu.dummy)
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        : [dummy] "=r" (fsu.dummy)
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    );
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    );
- 
 
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    return fsu.fs;
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    return fsu.fs;
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}
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}
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/** Returns FAR (fault address register) content.
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/** Returns FAR (fault address register) content.
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 *
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 *
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 * @return FAR (fault address register) content (address that caused a page
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 * @return FAR (fault address register) content (address that caused a page
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 *     fault)
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 *         fault)
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 */
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 */
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static inline uintptr_t read_fault_address_register(void)
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static inline uintptr_t read_fault_address_register(void)
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{
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{
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    uintptr_t ret;
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    uintptr_t ret;
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    /* fault adress is stored in CP15 register 6 */
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    /* fault adress is stored in CP15 register 6 */
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    asm volatile (
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    asm volatile (
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        "mrc p15, 0, %0, c6, c0, 0"
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        "mrc p15, 0, %[ret], c6, c0, 0"
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        : "=r"(ret)
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        : [ret] "=r" (ret)
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    );
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    );
- 
 
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    return ret;
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    return ret;
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}
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}
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/** Decides whether the instruction is load/store or not.
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/** Decides whether the instruction is load/store or not.
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 *
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 *
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 * @param instr Instruction
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 * @param instr Instruction
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 *
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 *
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 * @return true when instruction is load/store, false otherwise
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 * @return true when instruction is load/store, false otherwise
- 
 
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 *
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 */
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 */
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static inline bool is_load_store_instruction(instruction_t instr)
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static inline bool is_load_store_instruction(instruction_t instr)
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{
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{
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    /* load store immediate offset */
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    /* load store immediate offset */
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    if (instr.type == 0x2) {
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    if (instr.type == 0x2)
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        return true;
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        return true;
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    }
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 - 
 
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    /* load store register offset */
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    /* load store register offset */
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    if (instr.type == 0x3 && instr.bit4 == 0) {
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    if ((instr.type == 0x3) && (instr.bit4 == 0))
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        return true;
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        return true;
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    }
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 - 
 
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    /* load store multiple */
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    /* load store multiple */
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    if (instr.type == 0x4) {
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    if (instr.type == 0x4)
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        return true;
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        return true;
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    }
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 - 
 
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    /* oprocessor load/store */
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    /* oprocessor load/store */
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    if (instr.type == 0x6) {
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    if (instr.type == 0x6)
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        return true;
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        return true;
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    }
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 - 
 
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    return false;
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    return false;
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}
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}
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/** Decides whether the instruction is swap or not.
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/** Decides whether the instruction is swap or not.
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 *
 109 
 *
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 * @return true when instruction is swap, false otherwise
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 * @return true when instruction is swap, false otherwise
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 */
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 */
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static inline bool is_swap_instruction(instruction_t instr)
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static inline bool is_swap_instruction(instruction_t instr)
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{
 115 
{
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    /* swap, swapb instruction */
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    /* swap, swapb instruction */
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    if (instr.type == 0x0 &&
 117 
    if ((instr.type == 0x0) &&
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        (instr.opcode == 0x8 || instr.opcode == 0xa) &&
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        ((instr.opcode == 0x8) || (instr.opcode == 0xa)) &&
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        instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {
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        (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1))
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        return true;
 120 
        return true;
122 
    }
 121 
   
123 
 
 - 
 
124 
    return false;
 122 
    return false;
125 
}
 123 
}
126 
 
 124 
 
127 
/** Decides whether read or write into memory is requested.
 125 
/** Decides whether read or write into memory is requested.
128 
 *
 126 
 *