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36 | 36 | ||
37 | #ifndef LIBC_amd64_ATOMIC_H_ |
37 | #ifndef LIBC_amd64_ATOMIC_H_ |
38 | #define LIBC_amd64_ATOMIC_H_ |
38 | #define LIBC_amd64_ATOMIC_H_ |
39 | 39 | ||
40 | static inline void atomic_inc(atomic_t *val) { |
40 | static inline void atomic_inc(atomic_t *val) { |
41 | asm volatile ("lock incq %0\n" : "=m" (val->count)); |
41 | asm volatile ("lock incq %0\n" : "+m" (val->count)); |
42 | } |
42 | } |
43 | 43 | ||
44 | static inline void atomic_dec(atomic_t *val) { |
44 | static inline void atomic_dec(atomic_t *val) { |
45 | asm volatile ("lock decq %0\n" : "=m" (val->count)); |
45 | asm volatile ("lock decq %0\n" : "+m" (val->count)); |
46 | } |
46 | } |
47 | 47 | ||
48 | static inline long atomic_postinc(atomic_t *val) |
48 | static inline long atomic_postinc(atomic_t *val) |
49 | { |
49 | { |
50 | long r; |
50 | long r; |
51 | 51 | ||
52 | asm volatile ( |
52 | asm volatile ( |
53 | "movq $1, %0\n" |
53 | "movq $1, %0\n" |
54 | "lock xaddq %0, %1\n" |
54 | "lock xaddq %0, %1\n" |
55 | : "=r" (r), "=m" (val->count) |
55 | : "=r" (r), "+m" (val->count) |
56 | ); |
56 | ); |
57 | 57 | ||
58 | return r; |
58 | return r; |
59 | } |
59 | } |
60 | 60 | ||
Line 63... | Line 63... | ||
63 | long r; |
63 | long r; |
64 | 64 | ||
65 | asm volatile ( |
65 | asm volatile ( |
66 | "movq $-1, %0\n" |
66 | "movq $-1, %0\n" |
67 | "lock xaddq %0, %1\n" |
67 | "lock xaddq %0, %1\n" |
68 | : "=r" (r), "=m" (val->count) |
68 | : "=r" (r), "+m" (val->count) |
69 | ); |
69 | ); |
70 | 70 | ||
71 | return r; |
71 | return r; |
72 | } |
72 | } |
73 | 73 | ||
74 | #define atomic_preinc(val) (atomic_postinc(val)+1) |
74 | #define atomic_preinc(val) (atomic_postinc(val) + 1) |
75 | #define atomic_predec(val) (atomic_postdec(val)-1) |
75 | #define atomic_predec(val) (atomic_postdec(val) - 1) |
76 | 76 | ||
77 | #endif |
77 | #endif |
78 | 78 | ||
79 | /** @} |
79 | /** @} |
80 | */ |
80 | */ |