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Rev 3022 | Rev 4055 | ||
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Line 42... | Line 42... | ||
42 | * The structure of a notification message is as follows: |
42 | * The structure of a notification message is as follows: |
43 | * - METHOD: method as registered by the SYS_IPC_REGISTER_IRQ syscall |
43 | * - METHOD: method as registered by the SYS_IPC_REGISTER_IRQ syscall |
44 | * - ARG1: payload modified by a 'top-half' handler |
44 | * - ARG1: payload modified by a 'top-half' handler |
45 | * - ARG2: payload modified by a 'top-half' handler |
45 | * - ARG2: payload modified by a 'top-half' handler |
46 | * - ARG3: payload modified by a 'top-half' handler |
46 | * - ARG3: payload modified by a 'top-half' handler |
- | 47 | * - ARG4: payload modified by a 'top-half' handler |
|
- | 48 | * - ARG5: payload modified by a 'top-half' handler |
|
47 | * - in_phone_hash: interrupt counter (may be needed to assure correct order |
49 | * - in_phone_hash: interrupt counter (may be needed to assure correct order |
48 | * in multithreaded drivers) |
50 | * in multithreaded drivers) |
- | 51 | * |
|
- | 52 | * Note on synchronization for ipc_irq_register(), ipc_irq_unregister(), |
|
- | 53 | * ipc_irq_cleanup() and IRQ handlers: |
|
- | 54 | * |
|
- | 55 | * By always taking all of the uspace IRQ hash table lock, IRQ structure lock |
|
- | 56 | * and answerbox lock, we can rule out race conditions between the |
|
- | 57 | * registration functions and also the cleanup function. Thus the observer can |
|
- | 58 | * either see the IRQ structure present in both the hash table and the |
|
- | 59 | * answerbox list or absent in both. Views in which the IRQ structure would be |
|
- | 60 | * linked in the hash table but not in the answerbox list, or vice versa, are |
|
- | 61 | * not possible. |
|
- | 62 | * |
|
- | 63 | * By always taking the hash table lock and the IRQ structure lock, we can |
|
- | 64 | * rule out a scenario in which we would free up an IRQ structure, which is |
|
- | 65 | * still referenced by, for example, an IRQ handler. The locking scheme forces |
|
- | 66 | * us to lock the IRQ structure only after any progressing IRQs on that |
|
- | 67 | * structure are finished. Because we hold the hash table lock, we prevent new |
|
- | 68 | * IRQs from taking new references to the IRQ structure. |
|
49 | */ |
69 | */ |
50 | 70 | ||
51 | #include <arch.h> |
71 | #include <arch.h> |
52 | #include <mm/slab.h> |
72 | #include <mm/slab.h> |
53 | #include <errno.h> |
73 | #include <errno.h> |
Line 56... | Line 76... | ||
56 | #include <ipc/irq.h> |
76 | #include <ipc/irq.h> |
57 | #include <syscall/copy.h> |
77 | #include <syscall/copy.h> |
58 | #include <console/console.h> |
78 | #include <console/console.h> |
59 | #include <print.h> |
79 | #include <print.h> |
60 | 80 | ||
61 | /** Execute code associated with IRQ notification. |
- | |
62 | * |
- | |
63 | * @param call Notification call. |
- | |
64 | * @param code Top-half pseudocode. |
- | |
65 | */ |
- | |
66 | static void code_execute(call_t *call, irq_code_t *code) |
- | |
67 | { |
- | |
68 | unsigned int i; |
- | |
69 | unative_t dstval = 0; |
- | |
70 | - | ||
71 | if (!code) |
- | |
72 | return; |
- | |
73 | - | ||
74 | for (i = 0; i < code->cmdcount; i++) { |
- | |
75 | switch (code->cmds[i].cmd) { |
- | |
76 | case CMD_MEM_READ_1: |
- | |
77 | dstval = *((uint8_t *) code->cmds[i].addr); |
- | |
78 | break; |
- | |
79 | case CMD_MEM_READ_2: |
- | |
80 | dstval = *((uint16_t *) code->cmds[i].addr); |
- | |
81 | break; |
- | |
82 | case CMD_MEM_READ_4: |
- | |
83 | dstval = *((uint32_t *) code->cmds[i].addr); |
- | |
84 | break; |
- | |
85 | case CMD_MEM_READ_8: |
- | |
86 | dstval = *((uint64_t *) code->cmds[i].addr); |
- | |
87 | break; |
- | |
88 | case CMD_MEM_WRITE_1: |
- | |
89 | *((uint8_t *) code->cmds[i].addr) = code->cmds[i].value; |
- | |
90 | break; |
- | |
91 | case CMD_MEM_WRITE_2: |
- | |
92 | *((uint16_t *) code->cmds[i].addr) = |
- | |
93 | code->cmds[i].value; |
- | |
94 | break; |
- | |
95 | case CMD_MEM_WRITE_4: |
- | |
96 | *((uint32_t *) code->cmds[i].addr) = |
- | |
97 | code->cmds[i].value; |
- | |
98 | break; |
- | |
99 | case CMD_MEM_WRITE_8: |
- | |
100 | *((uint64_t *) code->cmds[i].addr) = |
- | |
101 | code->cmds[i].value; |
- | |
102 | break; |
- | |
103 | #if defined(ia32) || defined(amd64) |
- | |
104 | case CMD_PORT_READ_1: |
- | |
105 | dstval = inb((long) code->cmds[i].addr); |
- | |
106 | break; |
- | |
107 | case CMD_PORT_WRITE_1: |
- | |
108 | outb((long) code->cmds[i].addr, code->cmds[i].value); |
- | |
109 | break; |
- | |
110 | #endif |
- | |
111 | #if defined(ia64) && defined(SKI) |
- | |
112 | case CMD_IA64_GETCHAR: |
- | |
113 | dstval = _getc(&ski_uconsole); |
- | |
114 | break; |
- | |
115 | #endif |
- | |
116 | #if defined(ppc32) |
- | |
117 | case CMD_PPC32_GETCHAR: |
- | |
118 | dstval = cuda_get_scancode(); |
- | |
119 | break; |
- | |
120 | #endif |
- | |
121 | default: |
- | |
122 | break; |
- | |
123 | } |
- | |
124 | if (code->cmds[i].dstarg && code->cmds[i].dstarg < |
- | |
125 | IPC_CALL_LEN) { |
- | |
126 | call->data.args[code->cmds[i].dstarg] = dstval; |
- | |
127 | } |
- | |
128 | } |
- | |
129 | } |
- | |
130 | - | ||
131 | /** Free top-half pseudocode. |
81 | /** Free the top-half pseudocode. |
132 | * |
82 | * |
133 | * @param code Pointer to the top-half pseudocode. |
83 | * @param code Pointer to the top-half pseudocode. |
134 | */ |
84 | */ |
135 | static void code_free(irq_code_t *code) |
85 | static void code_free(irq_code_t *code) |
136 | { |
86 | { |
Line 138... | Line 88... | ||
138 | free(code->cmds); |
88 | free(code->cmds); |
139 | free(code); |
89 | free(code); |
140 | } |
90 | } |
141 | } |
91 | } |
142 | 92 | ||
143 | /** Copy top-half pseudocode from userspace into the kernel. |
93 | /** Copy the top-half pseudocode from userspace into the kernel. |
144 | * |
94 | * |
145 | * @param ucode Userspace address of the top-half pseudocode. |
95 | * @param ucode Userspace address of the top-half pseudocode. |
146 | * |
96 | * |
147 | * @return Kernel address of the copied pseudocode. |
97 | * @return Kernel address of the copied pseudocode. |
148 | */ |
98 | */ |
Line 174... | Line 124... | ||
174 | } |
124 | } |
175 | 125 | ||
176 | return code; |
126 | return code; |
177 | } |
127 | } |
178 | 128 | ||
179 | /** Unregister task from IRQ notification. |
- | |
180 | * |
- | |
181 | * @param box Answerbox associated with the notification. |
- | |
182 | * @param inr IRQ number. |
- | |
183 | * @param devno Device number. |
- | |
184 | */ |
- | |
185 | void ipc_irq_unregister(answerbox_t *box, inr_t inr, devno_t devno) |
- | |
186 | { |
- | |
187 | ipl_t ipl; |
- | |
188 | irq_t *irq; |
- | |
189 | - | ||
190 | ipl = interrupts_disable(); |
- | |
191 | irq = irq_find_and_lock(inr, devno); |
- | |
192 | if (irq) { |
- | |
193 | if (irq->notif_cfg.answerbox == box) { |
- | |
194 | code_free(irq->notif_cfg.code); |
- | |
195 | irq->notif_cfg.notify = false; |
- | |
196 | irq->notif_cfg.answerbox = NULL; |
- | |
197 | irq->notif_cfg.code = NULL; |
- | |
198 | irq->notif_cfg.method = 0; |
- | |
199 | irq->notif_cfg.counter = 0; |
- | |
200 | - | ||
201 | spinlock_lock(&box->irq_lock); |
- | |
202 | list_remove(&irq->notif_cfg.link); |
- | |
203 | spinlock_unlock(&box->irq_lock); |
- | |
204 | - | ||
205 | spinlock_unlock(&irq->lock); |
- | |
206 | } |
- | |
207 | } |
- | |
208 | interrupts_restore(ipl); |
- | |
209 | } |
- | |
210 | - | ||
211 | /** Register an answerbox as a receiving end for IRQ notifications. |
129 | /** Register an answerbox as a receiving end for IRQ notifications. |
212 | * |
130 | * |
213 | * @param box Receiving answerbox. |
131 | * @param box Receiving answerbox. |
214 | * @param inr IRQ number. |
132 | * @param inr IRQ number. |
215 | * @param devno Device number. |
133 | * @param devno Device number. |
Line 222... | Line 140... | ||
222 | unative_t method, irq_code_t *ucode) |
140 | unative_t method, irq_code_t *ucode) |
223 | { |
141 | { |
224 | ipl_t ipl; |
142 | ipl_t ipl; |
225 | irq_code_t *code; |
143 | irq_code_t *code; |
226 | irq_t *irq; |
144 | irq_t *irq; |
- | 145 | unative_t key[] = { |
|
- | 146 | (unative_t) inr, |
|
- | 147 | (unative_t) devno |
|
- | 148 | }; |
|
227 | 149 | ||
228 | if (ucode) { |
150 | if (ucode) { |
229 | code = code_from_uspace(ucode); |
151 | code = code_from_uspace(ucode); |
230 | if (!code) |
152 | if (!code) |
231 | return EBADMEM; |
153 | return EBADMEM; |
232 | } else { |
154 | } else { |
233 | code = NULL; |
155 | code = NULL; |
234 | } |
156 | } |
235 | 157 | ||
236 | ipl = interrupts_disable(); |
158 | /* |
237 | irq = irq_find_and_lock(inr, devno); |
159 | * Allocate and populate the IRQ structure. |
238 | if (!irq) { |
160 | */ |
239 | interrupts_restore(ipl); |
161 | irq = malloc(sizeof(irq_t), 0); |
240 | code_free(code); |
162 | irq_initialize(irq); |
241 | return ENOENT; |
163 | irq->devno = devno; |
242 | } |
- | |
243 | - | ||
244 | if (irq->notif_cfg.answerbox) { |
164 | irq->inr = inr; |
245 | spinlock_unlock(&irq->lock); |
165 | irq->claim = ipc_irq_top_half_claim; |
246 | interrupts_restore(ipl); |
166 | irq->handler = ipc_irq_top_half_handler; |
247 | code_free(code); |
- | |
248 | return EEXISTS; |
- | |
249 | } |
- | |
250 | - | ||
251 | irq->notif_cfg.notify = true; |
167 | irq->notif_cfg.notify = true; |
252 | irq->notif_cfg.answerbox = box; |
168 | irq->notif_cfg.answerbox = box; |
253 | irq->notif_cfg.method = method; |
169 | irq->notif_cfg.method = method; |
254 | irq->notif_cfg.code = code; |
170 | irq->notif_cfg.code = code; |
255 | irq->notif_cfg.counter = 0; |
171 | irq->notif_cfg.counter = 0; |
256 | 172 | ||
- | 173 | /* |
|
- | 174 | * Enlist the IRQ structure in the uspace IRQ hash table and the |
|
- | 175 | * answerbox's list. |
|
- | 176 | */ |
|
- | 177 | ipl = interrupts_disable(); |
|
- | 178 | spinlock_lock(&irq_uspace_hash_table_lock); |
|
- | 179 | spinlock_lock(&irq->lock); |
|
257 | spinlock_lock(&box->irq_lock); |
180 | spinlock_lock(&box->irq_lock); |
- | 181 | if (hash_table_find(&irq_uspace_hash_table, key)) { |
|
- | 182 | code_free(code); |
|
- | 183 | spinlock_unlock(&box->irq_lock); |
|
- | 184 | spinlock_unlock(&irq->lock); |
|
- | 185 | spinlock_unlock(&irq_uspace_hash_table_lock); |
|
- | 186 | free(irq); |
|
- | 187 | interrupts_restore(ipl); |
|
- | 188 | return EEXISTS; |
|
- | 189 | } |
|
- | 190 | hash_table_insert(&irq_uspace_hash_table, key, &irq->link); |
|
258 | list_append(&irq->notif_cfg.link, &box->irq_head); |
191 | list_append(&irq->notif_cfg.link, &box->irq_head); |
259 | spinlock_unlock(&box->irq_lock); |
192 | spinlock_unlock(&box->irq_lock); |
- | 193 | spinlock_unlock(&irq->lock); |
|
- | 194 | spinlock_unlock(&irq_uspace_hash_table_lock); |
|
260 | 195 | ||
- | 196 | interrupts_restore(ipl); |
|
- | 197 | return EOK; |
|
- | 198 | } |
|
- | 199 | ||
- | 200 | /** Unregister task from IRQ notification. |
|
- | 201 | * |
|
- | 202 | * @param box Answerbox associated with the notification. |
|
- | 203 | * @param inr IRQ number. |
|
- | 204 | * @param devno Device number. |
|
- | 205 | */ |
|
- | 206 | int ipc_irq_unregister(answerbox_t *box, inr_t inr, devno_t devno) |
|
- | 207 | { |
|
- | 208 | ipl_t ipl; |
|
- | 209 | unative_t key[] = { |
|
- | 210 | (unative_t) inr, |
|
- | 211 | (unative_t) devno |
|
- | 212 | }; |
|
- | 213 | link_t *lnk; |
|
- | 214 | irq_t *irq; |
|
- | 215 | ||
- | 216 | ipl = interrupts_disable(); |
|
- | 217 | spinlock_lock(&irq_uspace_hash_table_lock); |
|
- | 218 | lnk = hash_table_find(&irq_uspace_hash_table, key); |
|
- | 219 | if (!lnk) { |
|
- | 220 | spinlock_unlock(&irq_uspace_hash_table_lock); |
|
- | 221 | interrupts_restore(ipl); |
|
- | 222 | return ENOENT; |
|
- | 223 | } |
|
- | 224 | irq = hash_table_get_instance(lnk, irq_t, link); |
|
- | 225 | spinlock_lock(&irq->lock); |
|
- | 226 | spinlock_lock(&box->irq_lock); |
|
- | 227 | ||
- | 228 | ASSERT(irq->notif_cfg.answerbox == box); |
|
- | 229 | ||
- | 230 | /* Free up the pseudo code and associated structures. */ |
|
- | 231 | code_free(irq->notif_cfg.code); |
|
- | 232 | ||
- | 233 | /* Remove the IRQ from the answerbox's list. */ |
|
- | 234 | list_remove(&irq->notif_cfg.link); |
|
- | 235 | ||
- | 236 | /* Remove the IRQ from the uspace IRQ hash table. */ |
|
- | 237 | hash_table_remove(&irq_uspace_hash_table, key, 2); |
|
- | 238 | ||
- | 239 | spinlock_unlock(&irq_uspace_hash_table_lock); |
|
261 | spinlock_unlock(&irq->lock); |
240 | spinlock_unlock(&irq->lock); |
- | 241 | spinlock_unlock(&box->irq_lock); |
|
- | 242 | ||
- | 243 | /* Free up the IRQ structure. */ |
|
- | 244 | free(irq); |
|
- | 245 | ||
262 | interrupts_restore(ipl); |
246 | interrupts_restore(ipl); |
- | 247 | return EOK; |
|
- | 248 | } |
|
263 | 249 | ||
- | 250 | ||
- | 251 | /** Disconnect all IRQ notifications from an answerbox. |
|
- | 252 | * |
|
- | 253 | * This function is effective because the answerbox contains |
|
- | 254 | * list of all irq_t structures that are registered to |
|
- | 255 | * send notifications to it. |
|
- | 256 | * |
|
- | 257 | * @param box Answerbox for which we want to carry out the cleanup. |
|
- | 258 | */ |
|
- | 259 | void ipc_irq_cleanup(answerbox_t *box) |
|
- | 260 | { |
|
- | 261 | ipl_t ipl; |
|
- | 262 | ||
- | 263 | loop: |
|
- | 264 | ipl = interrupts_disable(); |
|
- | 265 | spinlock_lock(&irq_uspace_hash_table_lock); |
|
- | 266 | spinlock_lock(&box->irq_lock); |
|
- | 267 | ||
- | 268 | while (box->irq_head.next != &box->irq_head) { |
|
- | 269 | link_t *cur = box->irq_head.next; |
|
- | 270 | irq_t *irq; |
|
- | 271 | DEADLOCK_PROBE_INIT(p_irqlock); |
|
- | 272 | unative_t key[2]; |
|
- | 273 | ||
- | 274 | irq = list_get_instance(cur, irq_t, notif_cfg.link); |
|
- | 275 | if (!spinlock_trylock(&irq->lock)) { |
|
- | 276 | /* |
|
- | 277 | * Avoid deadlock by trying again. |
|
- | 278 | */ |
|
- | 279 | spinlock_unlock(&box->irq_lock); |
|
- | 280 | spinlock_unlock(&irq_uspace_hash_table_lock); |
|
- | 281 | interrupts_restore(ipl); |
|
- | 282 | DEADLOCK_PROBE(p_irqlock, DEADLOCK_THRESHOLD); |
|
- | 283 | goto loop; |
|
- | 284 | } |
|
- | 285 | key[0] = irq->inr; |
|
- | 286 | key[1] = irq->devno; |
|
- | 287 | ||
- | 288 | ||
- | 289 | ASSERT(irq->notif_cfg.answerbox == box); |
|
- | 290 | ||
- | 291 | /* Unlist from the answerbox. */ |
|
- | 292 | list_remove(&irq->notif_cfg.link); |
|
- | 293 | ||
- | 294 | /* Remove from the hash table. */ |
|
- | 295 | hash_table_remove(&irq_uspace_hash_table, key, 2); |
|
- | 296 | ||
- | 297 | /* Free up the pseudo code and associated structures. */ |
|
- | 298 | code_free(irq->notif_cfg.code); |
|
- | 299 | ||
- | 300 | spinlock_unlock(&irq->lock); |
|
264 | return 0; |
301 | free(irq); |
- | 302 | } |
|
- | 303 | ||
- | 304 | spinlock_unlock(&box->irq_lock); |
|
- | 305 | spinlock_unlock(&irq_uspace_hash_table_lock); |
|
- | 306 | interrupts_restore(ipl); |
|
265 | } |
307 | } |
266 | 308 | ||
267 | /** Add a call to the proper answerbox queue. |
309 | /** Add a call to the proper answerbox queue. |
268 | * |
310 | * |
269 | * Assume irq->lock is locked. |
311 | * Assume irq->lock is locked. |
Line 278... | Line 320... | ||
278 | spinlock_unlock(&irq->notif_cfg.answerbox->irq_lock); |
320 | spinlock_unlock(&irq->notif_cfg.answerbox->irq_lock); |
279 | 321 | ||
280 | waitq_wakeup(&irq->notif_cfg.answerbox->wq, WAKEUP_FIRST); |
322 | waitq_wakeup(&irq->notif_cfg.answerbox->wq, WAKEUP_FIRST); |
281 | } |
323 | } |
282 | 324 | ||
283 | /** Send notification message. |
325 | /** Apply the top-half pseudo code to find out whether to accept the IRQ or not. |
284 | * |
326 | * |
285 | * @param irq IRQ structure. |
327 | * @param irq IRQ structure. |
286 | * @param a1 Driver-specific payload argument. |
- | |
- | 328 | * |
|
287 | * @param a2 Driver-specific payload argument. |
329 | * @return IRQ_ACCEPT if the interrupt is accepted by the |
288 | * @param a3 Driver-specific payload argument. |
330 | * pseudocode. IRQ_DECLINE otherwise. |
289 | * @param a4 Driver-specific payload argument. |
- | |
290 | * @param a5 Driver-specific payload argument. |
- | |
291 | */ |
331 | */ |
292 | void ipc_irq_send_msg(irq_t *irq, unative_t a1, unative_t a2, unative_t a3, |
332 | irq_ownership_t ipc_irq_top_half_claim(irq_t *irq) |
293 | unative_t a4, unative_t a5) |
- | |
294 | { |
333 | { |
- | 334 | unsigned int i; |
|
295 | call_t *call; |
335 | unative_t dstval; |
296 | - | ||
297 | spinlock_lock(&irq->lock); |
336 | irq_code_t *code = irq->notif_cfg.code; |
- | 337 | unative_t *scratch = irq->notif_cfg.scratch; |
|
298 | 338 | ||
- | 339 | ||
299 | if (irq->notif_cfg.answerbox) { |
340 | if (!irq->notif_cfg.notify) |
300 | call = ipc_call_alloc(FRAME_ATOMIC); |
341 | return IRQ_DECLINE; |
- | 342 | ||
301 | if (!call) { |
343 | if (!code) |
302 | spinlock_unlock(&irq->lock); |
- | |
303 | return; |
344 | return IRQ_DECLINE; |
304 | } |
345 | |
305 | call->flags |= IPC_CALL_NOTIF; |
- | |
306 | IPC_SET_METHOD(call->data, irq->notif_cfg.method); |
- | |
307 | IPC_SET_ARG1(call->data, a1); |
- | |
308 | IPC_SET_ARG2(call->data, a2); |
- | |
309 | IPC_SET_ARG3(call->data, a3); |
- | |
310 | IPC_SET_ARG4(call->data, a4); |
- | |
311 | IPC_SET_ARG5(call->data, a5); |
346 | for (i = 0; i < code->cmdcount; i++) { |
312 | /* Put a counter to the message */ |
347 | unsigned int srcarg = code->cmds[i].srcarg; |
313 | call->priv = ++irq->notif_cfg.counter; |
348 | unsigned int dstarg = code->cmds[i].dstarg; |
314 | 349 | ||
- | 350 | if (srcarg >= IPC_CALL_LEN) |
|
- | 351 | break; |
|
- | 352 | if (dstarg >= IPC_CALL_LEN) |
|
- | 353 | break; |
|
- | 354 | ||
- | 355 | switch (code->cmds[i].cmd) { |
|
- | 356 | case CMD_PIO_READ_8: |
|
- | 357 | dstval = pio_read_8((ioport8_t *) code->cmds[i].addr); |
|
- | 358 | if (dstarg) |
|
- | 359 | scratch[dstarg] = dstval; |
|
- | 360 | break; |
|
- | 361 | case CMD_PIO_READ_16: |
|
- | 362 | dstval = pio_read_16((ioport16_t *) code->cmds[i].addr); |
|
- | 363 | if (dstarg) |
|
- | 364 | scratch[dstarg] = dstval; |
|
- | 365 | break; |
|
- | 366 | case CMD_PIO_READ_32: |
|
- | 367 | dstval = pio_read_32((ioport32_t *) code->cmds[i].addr); |
|
- | 368 | if (dstarg) |
|
- | 369 | scratch[dstarg] = dstval; |
|
- | 370 | break; |
|
- | 371 | case CMD_PIO_WRITE_8: |
|
- | 372 | pio_write_8((ioport8_t *) code->cmds[i].addr, |
|
- | 373 | (uint8_t) code->cmds[i].value); |
|
- | 374 | break; |
|
- | 375 | case CMD_PIO_WRITE_16: |
|
- | 376 | pio_write_16((ioport16_t *) code->cmds[i].addr, |
|
- | 377 | (uint16_t) code->cmds[i].value); |
|
- | 378 | break; |
|
- | 379 | case CMD_PIO_WRITE_32: |
|
- | 380 | pio_write_32((ioport32_t *) code->cmds[i].addr, |
|
- | 381 | (uint32_t) code->cmds[i].value); |
|
- | 382 | break; |
|
- | 383 | case CMD_BTEST: |
|
315 | send_call(irq, call); |
384 | if (srcarg && dstarg) { |
- | 385 | dstval = scratch[srcarg] & code->cmds[i].value; |
|
- | 386 | scratch[dstarg] = dstval; |
|
- | 387 | } |
|
- | 388 | break; |
|
- | 389 | case CMD_PREDICATE: |
|
- | 390 | if (srcarg && !scratch[srcarg]) { |
|
- | 391 | i += code->cmds[i].value; |
|
- | 392 | continue; |
|
- | 393 | } |
|
- | 394 | break; |
|
- | 395 | case CMD_ACCEPT: |
|
- | 396 | return IRQ_ACCEPT; |
|
- | 397 | break; |
|
- | 398 | case CMD_DECLINE: |
|
- | 399 | default: |
|
- | 400 | return IRQ_DECLINE; |
|
- | 401 | } |
|
316 | } |
402 | } |
- | 403 | ||
317 | spinlock_unlock(&irq->lock); |
404 | return IRQ_DECLINE; |
318 | } |
405 | } |
319 | 406 | ||
- | 407 | ||
320 | /** Notify a task that an IRQ had occurred. |
408 | /* IRQ top-half handler. |
321 | * |
409 | * |
322 | * We expect interrupts to be disabled and the irq->lock already held. |
410 | * We expect interrupts to be disabled and the irq->lock already held. |
323 | * |
411 | * |
324 | * @param irq IRQ structure. |
412 | * @param irq IRQ structure. |
325 | */ |
413 | */ |
326 | void ipc_irq_send_notif(irq_t *irq) |
414 | void ipc_irq_top_half_handler(irq_t *irq) |
327 | { |
415 | { |
328 | call_t *call; |
- | |
329 | - | ||
330 | ASSERT(irq); |
416 | ASSERT(irq); |
331 | 417 | ||
332 | if (irq->notif_cfg.answerbox) { |
418 | if (irq->notif_cfg.answerbox) { |
- | 419 | call_t *call; |
|
- | 420 | ||
333 | call = ipc_call_alloc(FRAME_ATOMIC); |
421 | call = ipc_call_alloc(FRAME_ATOMIC); |
334 | if (!call) { |
422 | if (!call) |
335 | return; |
423 | return; |
336 | } |
424 | |
337 | call->flags |= IPC_CALL_NOTIF; |
425 | call->flags |= IPC_CALL_NOTIF; |
338 | /* Put a counter to the message */ |
426 | /* Put a counter to the message */ |
339 | call->priv = ++irq->notif_cfg.counter; |
427 | call->priv = ++irq->notif_cfg.counter; |
- | 428 | ||
340 | /* Set up args */ |
429 | /* Set up args */ |
341 | IPC_SET_METHOD(call->data, irq->notif_cfg.method); |
430 | IPC_SET_METHOD(call->data, irq->notif_cfg.method); |
- | 431 | IPC_SET_ARG1(call->data, irq->notif_cfg.scratch[1]); |
|
- | 432 | IPC_SET_ARG2(call->data, irq->notif_cfg.scratch[2]); |
|
- | 433 | IPC_SET_ARG3(call->data, irq->notif_cfg.scratch[3]); |
|
- | 434 | IPC_SET_ARG4(call->data, irq->notif_cfg.scratch[4]); |
|
- | 435 | IPC_SET_ARG5(call->data, irq->notif_cfg.scratch[5]); |
|
342 | 436 | ||
343 | /* Execute code to handle irq */ |
- | |
344 | code_execute(call, irq->notif_cfg.code); |
- | |
345 | - | ||
346 | send_call(irq, call); |
437 | send_call(irq, call); |
347 | } |
438 | } |
348 | } |
439 | } |
349 | 440 | ||
350 | /** Disconnect all IRQ notifications from an answerbox. |
- | |
351 | * |
- | |
352 | * This function is effective because the answerbox contains |
- | |
353 | * list of all irq_t structures that are registered to |
- | |
354 | * send notifications to it. |
441 | /** Send notification message. |
355 | * |
442 | * |
- | 443 | * @param irq IRQ structure. |
|
- | 444 | * @param a1 Driver-specific payload argument. |
|
- | 445 | * @param a2 Driver-specific payload argument. |
|
356 | * @param box Answerbox for which we want to carry out the cleanup. |
446 | * @param a3 Driver-specific payload argument. |
- | 447 | * @param a4 Driver-specific payload argument. |
|
- | 448 | * @param a5 Driver-specific payload argument. |
|
357 | */ |
449 | */ |
- | 450 | void ipc_irq_send_msg(irq_t *irq, unative_t a1, unative_t a2, unative_t a3, |
|
358 | void ipc_irq_cleanup(answerbox_t *box) |
451 | unative_t a4, unative_t a5) |
359 | { |
452 | { |
360 | ipl_t ipl; |
453 | call_t *call; |
361 | 454 | ||
362 | loop: |
- | |
363 | ipl = interrupts_disable(); |
- | |
364 | spinlock_lock(&box->irq_lock); |
455 | spinlock_lock(&irq->lock); |
365 | 456 | ||
366 | while (box->irq_head.next != &box->irq_head) { |
457 | if (irq->notif_cfg.answerbox) { |
367 | link_t *cur = box->irq_head.next; |
458 | call = ipc_call_alloc(FRAME_ATOMIC); |
368 | irq_t *irq; |
459 | if (!call) { |
369 | DEADLOCK_PROBE_INIT(p_irqlock); |
- | |
370 | - | ||
371 | irq = list_get_instance(cur, irq_t, notif_cfg.link); |
- | |
372 | if (!spinlock_trylock(&irq->lock)) { |
- | |
373 | /* |
- | |
374 | * Avoid deadlock by trying again. |
- | |
375 | */ |
- | |
376 | spinlock_unlock(&box->irq_lock); |
460 | spinlock_unlock(&irq->lock); |
377 | interrupts_restore(ipl); |
- | |
378 | DEADLOCK_PROBE(p_irqlock, DEADLOCK_THRESHOLD); |
- | |
379 | goto loop; |
461 | return; |
380 | } |
462 | } |
381 | - | ||
382 | ASSERT(irq->notif_cfg.answerbox == box); |
- | |
383 | - | ||
384 | list_remove(&irq->notif_cfg.link); |
463 | call->flags |= IPC_CALL_NOTIF; |
385 | - | ||
386 | /* |
- | |
387 | * Don't forget to free any top-half pseudocode. |
464 | /* Put a counter to the message */ |
388 | */ |
- | |
389 | code_free(irq->notif_cfg.code); |
465 | call->priv = ++irq->notif_cfg.counter; |
390 | - | ||
391 | irq->notif_cfg.notify = false; |
- | |
392 | irq->notif_cfg.answerbox = NULL; |
- | |
393 | irq->notif_cfg.code = NULL; |
- | |
394 | irq->notif_cfg.method = 0; |
- | |
395 | irq->notif_cfg.counter = 0; |
- | |
396 | 466 | ||
- | 467 | IPC_SET_METHOD(call->data, irq->notif_cfg.method); |
|
- | 468 | IPC_SET_ARG1(call->data, a1); |
|
- | 469 | IPC_SET_ARG2(call->data, a2); |
|
- | 470 | IPC_SET_ARG3(call->data, a3); |
|
- | 471 | IPC_SET_ARG4(call->data, a4); |
|
- | 472 | IPC_SET_ARG5(call->data, a5); |
|
- | 473 | ||
397 | spinlock_unlock(&irq->lock); |
474 | send_call(irq, call); |
398 | } |
475 | } |
399 | - | ||
400 | spinlock_unlock(&box->irq_lock); |
476 | spinlock_unlock(&irq->lock); |
401 | interrupts_restore(ipl); |
- | |
402 | } |
477 | } |
403 | 478 | ||
404 | /** @} |
479 | /** @} |
405 | */ |
480 | */ |