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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | /** @addtogroup genarch |
29 | /** @addtogroup genarch |
| 30 | * @{ |
30 | * @{ |
| 31 | */ |
31 | */ |
| 32 | /** |
32 | /** |
| 33 | * @file |
33 | * @file |
| 34 | * @brief Headers for Zilog 8530 serial controller. |
34 | * @brief Headers for Zilog 8530 serial controller. |
| 35 | */ |
35 | */ |
| 36 | 36 | ||
| 37 | #ifndef KERN_Z8530_H_ |
37 | #ifndef KERN_Z8530_H_ |
| 38 | #define KERN_Z8530_H_ |
38 | #define KERN_Z8530_H_ |
| 39 | 39 | ||
| 40 | #include <ddi/irq.h> |
40 | #include <ddi/irq.h> |
| 41 | #include <arch/types.h> |
41 | #include <arch/types.h> |
| 42 | #include <console/chardev.h> |
42 | #include <console/chardev.h> |
| 43 | 43 | ||
| 44 | #define WR0 0 |
44 | #define WR0 0 |
| 45 | #define WR1 1 |
45 | #define WR1 1 |
| 46 | #define WR2 2 |
46 | #define WR2 2 |
| 47 | #define WR3 3 |
47 | #define WR3 3 |
| 48 | #define WR4 4 |
48 | #define WR4 4 |
| 49 | #define WR5 5 |
49 | #define WR5 5 |
| 50 | #define WR6 6 |
50 | #define WR6 6 |
| 51 | #define WR7 7 |
51 | #define WR7 7 |
| 52 | #define WR8 8 |
52 | #define WR8 8 |
| 53 | #define WR9 9 |
53 | #define WR9 9 |
| 54 | #define WR10 10 |
54 | #define WR10 10 |
| 55 | #define WR11 11 |
55 | #define WR11 11 |
| 56 | #define WR12 12 |
56 | #define WR12 12 |
| 57 | #define WR13 13 |
57 | #define WR13 13 |
| 58 | #define WR14 14 |
58 | #define WR14 14 |
| 59 | #define WR15 15 |
59 | #define WR15 15 |
| 60 | 60 | ||
| 61 | #define RR0 0 |
61 | #define RR0 0 |
| 62 | #define RR1 1 |
62 | #define RR1 1 |
| 63 | #define RR2 2 |
63 | #define RR2 2 |
| 64 | #define RR3 3 |
64 | #define RR3 3 |
| 65 | #define RR8 8 |
65 | #define RR8 8 |
| 66 | #define RR10 10 |
66 | #define RR10 10 |
| 67 | #define RR12 12 |
67 | #define RR12 12 |
| 68 | #define RR13 13 |
68 | #define RR13 13 |
| 69 | #define RR14 14 |
69 | #define RR14 14 |
| 70 | #define RR15 15 |
70 | #define RR15 15 |
| 71 | 71 | ||
| 72 | /** Reset pending TX interrupt. */ |
72 | /** Reset pending TX interrupt. */ |
| 73 | #define WR0_TX_IP_RST (0x5 << 3) |
73 | #define WR0_TX_IP_RST (0x5 << 3) |
| 74 | #define WR0_ERR_RST (0x6 << 3) |
74 | #define WR0_ERR_RST (0x6 << 3) |
| 75 | 75 | ||
| 76 | /** Receive Interrupts Disabled. */ |
76 | /** Receive Interrupts Disabled. */ |
| 77 | #define WR1_RID (0x0 << 3) |
77 | #define WR1_RID (0x0 << 3) |
| 78 | /** Receive Interrupt on First Character or Special Condition. */ |
78 | /** Receive Interrupt on First Character or Special Condition. */ |
| 79 | #define WR1_RIFCSC (0x1 << 3) |
79 | #define WR1_RIFCSC (0x1 << 3) |
| 80 | /** Interrupt on All Receive Characters or Special Conditions. */ |
80 | /** Interrupt on All Receive Characters or Special Conditions. */ |
| 81 | #define WR1_IARCSC (0x2 << 3) |
81 | #define WR1_IARCSC (0x2 << 3) |
| 82 | /** Receive Interrupt on Special Condition. */ |
82 | /** Receive Interrupt on Special Condition. */ |
| 83 | #define WR1_RISC (0x3 << 3) |
83 | #define WR1_RISC (0x3 << 3) |
| 84 | /** Parity Is Special Condition. */ |
84 | /** Parity Is Special Condition. */ |
| 85 | #define WR1_PISC (0x1 << 2) |
85 | #define WR1_PISC (0x1 << 2) |
| 86 | 86 | ||
| 87 | /** Rx Enable. */ |
87 | /** Rx Enable. */ |
| 88 | #define WR3_RX_ENABLE (0x1 << 0) |
88 | #define WR3_RX_ENABLE (0x1 << 0) |
| 89 | /** 8-bits per character. */ |
89 | /** 8-bits per character. */ |
| 90 | #define WR3_RX8BITSCH (0x3 << 6) |
90 | #define WR3_RX8BITSCH (0x3 << 6) |
| 91 | 91 | ||
| 92 | /** Master Interrupt Enable. */ |
92 | /** Master Interrupt Enable. */ |
| 93 | #define WR9_MIE (0x1 << 3) |
93 | #define WR9_MIE (0x1 << 3) |
| 94 | 94 | ||
| 95 | /** Receive Character Available. */ |
95 | /** Receive Character Available. */ |
| 96 | #define RR0_RCA (0x1 << 0) |
96 | #define RR0_RCA (0x1 << 0) |
| 97 | 97 | ||
| 98 | /** z8530's registers. */ |
98 | /** z8530's registers. */ |
| 99 | struct z8530 { |
99 | typedef struct { |
| 100 | union { |
100 | union { |
| 101 | ioport8_t ctl_b; |
101 | ioport8_t ctl_b; |
| 102 | ioport8_t status_b; |
102 | ioport8_t status_b; |
| 103 | } __attribute__ ((packed)); |
103 | } __attribute__ ((packed)); |
| 104 | uint8_t pad1; |
104 | uint8_t pad1; |
| Line 108... | Line 108... | ||
| 108 | ioport8_t ctl_a; |
108 | ioport8_t ctl_a; |
| 109 | ioport8_t status_a; |
109 | ioport8_t status_a; |
| 110 | } __attribute__ ((packed)); |
110 | } __attribute__ ((packed)); |
| 111 | uint8_t pad3; |
111 | uint8_t pad3; |
| 112 | ioport8_t data_a; |
112 | ioport8_t data_a; |
| 113 | } __attribute__ ((packed)); |
113 | } __attribute__ ((packed)) z8530_t; |
| 114 | typedef struct z8530 z8530_t; |
- | |
| 115 | 114 | ||
| 116 | /** Structure representing the z8530 device. */ |
115 | /** Structure representing the z8530 device. */ |
| 117 | typedef struct { |
116 | typedef struct { |
| 118 | devno_t devno; |
- | |
| 119 | irq_t irq; |
117 | irq_t irq; |
| 120 | z8530_t *z8530; |
118 | z8530_t *z8530; |
| 121 | chardev_t *devout; |
119 | indev_t kbrdin; |
| 122 | } z8530_instance_t; |
120 | } z8530_instance_t; |
| 123 | 121 | ||
| 124 | extern bool z8530_init(z8530_t *, devno_t, inr_t, cir_t, void *, chardev_t *); |
122 | extern indev_t *z8530_init(z8530_t *, inr_t, cir_t, void *); |
| 125 | extern irq_ownership_t z8530_claim(irq_t *); |
- | |
| 126 | extern void z8530_irq_handler(irq_t *); |
- | |
| 127 | 123 | ||
| 128 | #endif |
124 | #endif |
| 129 | 125 | ||
| 130 | /** @} |
126 | /** @} |
| 131 | */ |
127 | */ |