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Rev 3022 Rev 4055
Line 74... Line 74...
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    as->arch.itsb = (tsb_entry_t *) tsb;
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    as->arch.itsb = (tsb_entry_t *) tsb;
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    as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
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    as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
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        sizeof(tsb_entry_t));
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        sizeof(tsb_entry_t));
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    memsetb((uintptr_t) as->arch.itsb,
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    memsetb(as->arch.itsb,
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        (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);
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        (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);
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#endif
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#endif
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    return 0;
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    return 0;
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}
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}
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    tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
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    tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
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    itsb_base_write(tsb_base.value);
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    itsb_base_write(tsb_base.value);
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    tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
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    tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
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    dtsb_base_write(tsb_base.value);
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    dtsb_base_write(tsb_base.value);
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#if defined (US3)
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    /*
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     * Clear the extension registers.
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     * In HelenOS, primary and secondary context registers contain
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     * equal values and kernel misses (context 0, ie. the nucleus context)
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     * are excluded from the TSB miss handler, so it makes no sense
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     * to have separate TSBs for primary, secondary and nucleus contexts.
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     * Clearing the extension registers will ensure that the value of the
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     * TSB Base register will be used as an address of TSB, making the code
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     * compatible with the US port.
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     */
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    itsb_primary_extension_write(0);
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    itsb_nucleus_extension_write(0);
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    dtsb_primary_extension_write(0);
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    dtsb_secondary_extension_write(0);
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    dtsb_nucleus_extension_write(0);
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#endif
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#endif
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#endif
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}
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}
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/** Perform sparc64-specific tasks when an address space is removed from the
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/** Perform sparc64-specific tasks when an address space is removed from the
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 * processor.
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 * processor.