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| Rev 3022 | Rev 4055 | ||
|---|---|---|---|
| Line 73... | Line 73... | ||
| 73 | } |
73 | } |
| 74 | 74 | ||
| 75 | l_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, |
75 | l_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, |
| 76 | FRAME_ATOMIC | FRAME_KA); |
76 | FRAME_ATOMIC | FRAME_KA); |
| 77 | if (!l_apic_address) |
77 | if (!l_apic_address) |
| 78 | panic("cannot allocate address for l_apic\n"); |
78 | panic("Cannot allocate address for l_apic."); |
| 79 | 79 | ||
| 80 | io_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, |
80 | io_apic_address = (uintptr_t) frame_alloc(ONE_FRAME, |
| 81 | FRAME_ATOMIC | FRAME_KA); |
81 | FRAME_ATOMIC | FRAME_KA); |
| 82 | if (!io_apic_address) |
82 | if (!io_apic_address) |
| 83 | panic("cannot allocate address for io_apic\n"); |
83 | panic("Cannot allocate address for io_apic."); |
| 84 | 84 | ||
| 85 | if (config.cpu_count > 1) { |
85 | if (config.cpu_count > 1) { |
| 86 | page_mapping_insert(AS_KERNEL, l_apic_address, |
86 | page_mapping_insert(AS_KERNEL, l_apic_address, |
| 87 | (uintptr_t) l_apic, PAGE_NOT_CACHEABLE | PAGE_WRITE); |
87 | (uintptr_t) l_apic, PAGE_NOT_CACHEABLE | PAGE_WRITE); |
| 88 | page_mapping_insert(AS_KERNEL, io_apic_address, |
88 | page_mapping_insert(AS_KERNEL, io_apic_address, |
| Line 120... | Line 120... | ||
| 120 | 120 | ||
| 121 | /* |
121 | /* |
| 122 | * Save 0xa to address 0xf of the CMOS RAM. |
122 | * Save 0xa to address 0xf of the CMOS RAM. |
| 123 | * BIOS will not do the POST after the INIT signal. |
123 | * BIOS will not do the POST after the INIT signal. |
| 124 | */ |
124 | */ |
| 125 | outb(0x70, 0xf); |
125 | pio_write_8((ioport8_t *)0x70, 0xf); |
| 126 | outb(0x71, 0xa); |
126 | pio_write_8((ioport8_t *)0x71, 0xa); |
| 127 | 127 | ||
| 128 | pic_disable_irqs(0xffff); |
128 | pic_disable_irqs(0xffff); |
| 129 | apic_init(); |
129 | apic_init(); |
| 130 | 130 | ||
| 131 | uint8_t apic = l_apic_id(); |
131 | uint8_t apic = l_apic_id(); |
| Line 152... | Line 152... | ||
| 152 | } |
152 | } |
| 153 | 153 | ||
| 154 | /* |
154 | /* |
| 155 | * Prepare new GDT for CPU in question. |
155 | * Prepare new GDT for CPU in question. |
| 156 | */ |
156 | */ |
| - | 157 | ||
| - | 158 | /* XXX Flag FRAME_LOW_4_GiB was removed temporarily, |
|
| - | 159 | * it needs to be replaced by a generic fuctionality of |
|
| - | 160 | * the memory subsystem |
|
| - | 161 | */ |
|
| 157 | gdt_new = (struct descriptor *) malloc(GDT_ITEMS * |
162 | gdt_new = (struct descriptor *) malloc(GDT_ITEMS * |
| 158 | sizeof(struct descriptor), FRAME_ATOMIC); |
163 | sizeof(struct descriptor), FRAME_ATOMIC); |
| 159 | if (!gdt_new) |
164 | if (!gdt_new) |
| 160 | panic("couldn't allocate memory for GDT\n"); |
165 | panic("Cannot allocate memory for GDT."); |
| 161 | 166 | ||
| 162 | memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(struct descriptor)); |
167 | memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(struct descriptor)); |
| 163 | memsetb((uintptr_t)(&gdt_new[TSS_DES]), |
- | |
| 164 | sizeof(struct descriptor), 0); |
168 | memsetb(&gdt_new[TSS_DES], sizeof(struct descriptor), 0); |
| 165 | protected_ap_gdtr.limit = GDT_ITEMS * sizeof(struct descriptor); |
169 | protected_ap_gdtr.limit = GDT_ITEMS * sizeof(struct descriptor); |
| 166 | protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new); |
170 | protected_ap_gdtr.base = KA2PA((uintptr_t) gdt_new); |
| 167 | gdtr.base = (uintptr_t) gdt_new; |
171 | gdtr.base = (uintptr_t) gdt_new; |
| 168 | 172 | ||
| 169 | if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) { |
173 | if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) { |