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51 | #include <arch.h> |
51 | #include <arch.h> |
52 | #include <time/delay.h> |
52 | #include <time/delay.h> |
53 | #include <ddi/irq.h> |
53 | #include <ddi/irq.h> |
54 | #include <ddi/device.h> |
54 | #include <ddi/device.h> |
55 | 55 | ||
56 | #define CLK_PORT1 0x40 |
56 | #define CLK_PORT1 ((ioport8_t *)0x40) |
57 | #define CLK_PORT4 0x43 |
57 | #define CLK_PORT4 ((ioport8_t *)0x43) |
58 | 58 | ||
59 | #define CLK_CONST 1193180 |
59 | #define CLK_CONST 1193180 |
60 | #define MAGIC_NUMBER 1194 |
60 | #define MAGIC_NUMBER 1194 |
61 | 61 | ||
62 | static irq_t i8254_irq; |
62 | static irq_t i8254_irq; |
63 | 63 | ||
64 | static irq_ownership_t i8254_claim(void) |
64 | static irq_ownership_t i8254_claim(irq_t *irq) |
65 | { |
65 | { |
66 | return IRQ_ACCEPT; |
66 | return IRQ_ACCEPT; |
67 | } |
67 | } |
68 | 68 | ||
69 | static void i8254_irq_handler(irq_t *irq, void *arg __attribute__((unused)), ...) |
69 | static void i8254_irq_handler(irq_t *irq) |
70 | { |
70 | { |
71 | /* |
71 | /* |
72 | * This IRQ is responsible for kernel preemption. |
72 | * This IRQ is responsible for kernel preemption. |
73 | * Nevertheless, we are now holding a spinlock which prevents |
73 | * Nevertheless, we are now holding a spinlock which prevents |
74 | * preemption. For this particular IRQ, we don't need the |
74 | * preemption. For this particular IRQ, we don't need the |
Line 92... | Line 92... | ||
92 | i8254_normal_operation(); |
92 | i8254_normal_operation(); |
93 | } |
93 | } |
94 | 94 | ||
95 | void i8254_normal_operation(void) |
95 | void i8254_normal_operation(void) |
96 | { |
96 | { |
97 | outb(CLK_PORT4, 0x36); |
97 | pio_write_8(CLK_PORT4, 0x36); |
98 | pic_disable_irqs(1 << IRQ_CLK); |
98 | pic_disable_irqs(1 << IRQ_CLK); |
99 | outb(CLK_PORT1, (CLK_CONST / HZ) & 0xf); |
99 | pio_write_8(CLK_PORT1, (CLK_CONST / HZ) & 0xf); |
100 | outb(CLK_PORT1, (CLK_CONST / HZ) >> 8); |
100 | pio_write_8(CLK_PORT1, (CLK_CONST / HZ) >> 8); |
101 | pic_enable_irqs(1 << IRQ_CLK); |
101 | pic_enable_irqs(1 << IRQ_CLK); |
102 | } |
102 | } |
103 | 103 | ||
104 | #define LOOPS 150000 |
104 | #define LOOPS 150000 |
105 | #define SHIFT 11 |
105 | #define SHIFT 11 |
Line 112... | Line 112... | ||
112 | 112 | ||
113 | /* |
113 | /* |
114 | * One-shot timer. Count-down from 0xffff at 1193180Hz |
114 | * One-shot timer. Count-down from 0xffff at 1193180Hz |
115 | * MAGIC_NUMBER is the magic value for 1ms. |
115 | * MAGIC_NUMBER is the magic value for 1ms. |
116 | */ |
116 | */ |
117 | outb(CLK_PORT4, 0x30); |
117 | pio_write_8(CLK_PORT4, 0x30); |
118 | outb(CLK_PORT1, 0xff); |
118 | pio_write_8(CLK_PORT1, 0xff); |
119 | outb(CLK_PORT1, 0xff); |
119 | pio_write_8(CLK_PORT1, 0xff); |
120 | 120 | ||
121 | do { |
121 | do { |
122 | /* will read both status and count */ |
122 | /* will read both status and count */ |
123 | outb(CLK_PORT4, 0xc2); |
123 | pio_write_8(CLK_PORT4, 0xc2); |
124 | not_ok = (uint8_t) ((inb(CLK_PORT1) >> 6) & 1); |
124 | not_ok = (uint8_t) ((pio_read_8(CLK_PORT1) >> 6) & 1); |
125 | t1 = inb(CLK_PORT1); |
125 | t1 = pio_read_8(CLK_PORT1); |
126 | t1 |= inb(CLK_PORT1) << 8; |
126 | t1 |= pio_read_8(CLK_PORT1) << 8; |
127 | } while (not_ok); |
127 | } while (not_ok); |
128 | 128 | ||
129 | asm_delay_loop(LOOPS); |
129 | asm_delay_loop(LOOPS); |
130 | 130 | ||
131 | outb(CLK_PORT4, 0xd2); |
131 | pio_write_8(CLK_PORT4, 0xd2); |
132 | t2 = inb(CLK_PORT1); |
132 | t2 = pio_read_8(CLK_PORT1); |
133 | t2 |= inb(CLK_PORT1) << 8; |
133 | t2 |= pio_read_8(CLK_PORT1) << 8; |
134 | 134 | ||
135 | /* |
135 | /* |
136 | * We want to determine the overhead of the calibrating mechanism. |
136 | * We want to determine the overhead of the calibrating mechanism. |
137 | */ |
137 | */ |
138 | outb(CLK_PORT4, 0xd2); |
138 | pio_write_8(CLK_PORT4, 0xd2); |
139 | o1 = inb(CLK_PORT1); |
139 | o1 = pio_read_8(CLK_PORT1); |
140 | o1 |= inb(CLK_PORT1) << 8; |
140 | o1 |= pio_read_8(CLK_PORT1) << 8; |
141 | 141 | ||
142 | asm_fake_loop(LOOPS); |
142 | asm_fake_loop(LOOPS); |
143 | 143 | ||
144 | outb(CLK_PORT4, 0xd2); |
144 | pio_write_8(CLK_PORT4, 0xd2); |
145 | o2 = inb(CLK_PORT1); |
145 | o2 = pio_read_8(CLK_PORT1); |
146 | o2 |= inb(CLK_PORT1) << 8; |
146 | o2 |= pio_read_8(CLK_PORT1) << 8; |
147 | 147 | ||
148 | CPU->delay_loop_const = |
148 | CPU->delay_loop_const = |
149 | ((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) + |
149 | ((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) + |
150 | (((MAGIC_NUMBER * LOOPS) / 1000) % ((t1 - t2) - (o1 - o2)) ? 1 : 0); |
150 | (((MAGIC_NUMBER * LOOPS) / 1000) % ((t1 - t2) - (o1 - o2)) ? 1 : 0); |
151 | 151 |