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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup ia32   
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/** @addtogroup ia32
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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/*
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/*
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 * Provisions are made to prevent compiler from reordering instructions itself.
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 * Provisions are made to prevent compiler from reordering instructions itself.
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 */
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 */
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#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
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#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
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#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
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#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
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static inline void cpuid_serialization(void)
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static inline void cpuid_serialization(void)
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{
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{
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    asm volatile (
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    asm volatile (
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        "xorl %%eax, %%eax\n"
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        "xorl %%eax, %%eax\n"
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        "cpuid\n"
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        "cpuid\n"
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        ::: "eax", "ebx", "ecx", "edx", "memory"
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        ::: "eax", "ebx", "ecx", "edx", "memory"
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    );
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    );
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}
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}
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#ifdef CONFIG_FENCES_P4
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#if defined(CONFIG_FENCES_P4)
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#   define memory_barrier()     asm volatile ("mfence\n" ::: "memory")
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    #define memory_barrier()  asm volatile ("mfence\n" ::: "memory")
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#   define read_barrier()       asm volatile ("lfence\n" ::: "memory")
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    #define read_barrier()    asm volatile ("lfence\n" ::: "memory")
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#   ifdef CONFIG_WEAK_MEMORY
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    #ifdef CONFIG_WEAK_MEMORY
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#       define write_barrier()  asm volatile ("sfence\n" ::: "memory")
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        #define write_barrier()  asm volatile ("sfence\n" ::: "memory")
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#   else
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    #else
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#       define write_barrier()  asm volatile( "" ::: "memory");
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        #define write_barrier()  asm volatile ("" ::: "memory");
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#   endif
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    #endif
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#elif CONFIG_FENCES_P3
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#elif defined(CONFIG_FENCES_P3)
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#   define memory_barrier()     cpuid_serialization()
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    #define memory_barrier()  cpuid_serialization()
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#   define read_barrier()       cpuid_serialization()
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    #define read_barrier()    cpuid_serialization()
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#   ifdef CONFIG_WEAK_MEMORY
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    #ifdef CONFIG_WEAK_MEMORY
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#       define write_barrier()  asm volatile ("sfence\n" ::: "memory")
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        #define write_barrier()  asm volatile ("sfence\n" ::: "memory")
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#   else
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    #else
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#       define write_barrier()  asm volatile( "" ::: "memory");
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        #define write_barrier()  asm volatile ("" ::: "memory");
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#   endif
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    #endif
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#else
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#else
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#   define memory_barrier()     cpuid_serialization()
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    #define memory_barrier()  cpuid_serialization()
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#   define read_barrier()       cpuid_serialization()
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    #define read_barrier()    cpuid_serialization()
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#   ifdef CONFIG_WEAK_MEMORY
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    #ifdef CONFIG_WEAK_MEMORY
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#       define write_barrier()  cpuid_serialization()
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        #define write_barrier()  cpuid_serialization()
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#   else
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    #else
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#       define write_barrier()  asm volatile( "" ::: "memory");
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        #define write_barrier()  asm volatile ("" ::: "memory");
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#   endif
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    #endif
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#endif
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#endif
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- 
 
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/*
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 * On ia32, the hardware takes care about instruction and data cache coherence,
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 * even on SMP systems.  We issue a write barrier to be sure that writes
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 * queueing in the store buffer drain to the memory (even though it would be
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 * sufficient for them to drain to the D-cache).
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 */
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#define smc_coherence(a)           write_barrier()
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#define smc_coherence_block(a, l)  write_barrier()
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#endif
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#endif
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/** @}
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/** @}
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 */
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 */