WebSVN – HelenOS – Diff – /branches/dd/kernel/arch/arm32/src/exception.c

 #include <arch/memstr.h>
 #include <arch/regutils.h>
 #include <interrupt.h>
 #include <arch/machine.h>
 #include <arch/mm/page_fault.h>
+#include <arch/barrier.h>
 #include <print.h>
 #include <syscall/syscall.h>
 /** Offset used in calculation of exception handler's relative address.
+ *
 /** Switches to kernel stack and saves all registers there.
+ *
  * Temporary exception stack is used to save a few registers
  * before stack switch takes place.
+ *
  */
 inline static void setup_stack_and_save_regs()
+{
-    asm volatile(
+    asm volatile (
-        "ldr r13, =exc_stack        \n"
+        "ldr r13, =exc_stack\n"
-        "stmfd r13!, {r0}       \n"
+        "stmfd r13!, {r0}\n"
-        "mrs r0, spsr           \n"
+        "mrs r0, spsr\n"
-        "and r0, r0, #0x1f      \n"
+        "and r0, r0, #0x1f\n"
-        "cmp r0, #0x10          \n"
+        "cmp r0, #0x10\n"
-        "bne 1f             \n"
+        "bne 1f\n"
         /* prev mode was usermode */
-        "ldmfd r13!, {r0}       \n"
+        "ldmfd r13!, {r0}\n"
-        "ldr r13, =supervisor_sp    \n"
+        "ldr r13, =supervisor_sp\n"
-        "ldr r13, [r13]         \n"
+        "ldr r13, [r13]\n"
-        "stmfd r13!, {lr}       \n"
+        "stmfd r13!, {lr}\n"
-        "stmfd r13!, {r0-r12}       \n"
+        "stmfd r13!, {r0-r12}\n"
-        "stmfd r13!, {r13, lr}^     \n"
+        "stmfd r13!, {r13, lr}^\n"
-        "mrs r0, spsr           \n"
+        "mrs r0, spsr\n"
-        "stmfd r13!, {r0}       \n"
+        "stmfd r13!, {r0}\n"
-        "b 2f               \n"
+        "b 2f\n"
         /* mode was not usermode */
-    "1:\n"
+        "1:\n"
-        "stmfd r13!, {r1, r2, r3}   \n"
+            "stmfd r13!, {r1, r2, r3}\n"
-        "mrs r1, cpsr           \n"
+            "mrs r1, cpsr\n"
-        "mov r2, lr         \n"
+            "mov r2, lr\n"
-        "bic r1, r1, #0x1f      \n"
+            "bic r1, r1, #0x1f\n"
-        "orr r1, r1, r0         \n"
+            "orr r1, r1, r0\n"
-        "mrs r0, cpsr           \n"
+            "mrs r0, cpsr\n"
-        "msr cpsr_c, r1         \n"
+            "msr cpsr_c, r1\n"
-        "mov r3, r13            \n"
+            "mov r3, r13\n"
-        "stmfd r13!, {r2}       \n"
+            "stmfd r13!, {r2}\n"
-        "mov r2, lr         \n"
+            "mov r2, lr\n"
-        "stmfd r13!, {r4-r12}       \n"
+            "stmfd r13!, {r4-r12}\n"
-        "mov r1, r13            \n"
+            "mov r1, r13\n"
-        /* the following two lines are for debugging */
+            /* the following two lines are for debugging */
-        "mov sp, #0         \n"
+            "mov sp, #0\n"
-        "mov lr, #0         \n"
+            "mov lr, #0\n"
-        "msr cpsr_c, r0         \n"
+            "msr cpsr_c, r0\n"
-        "ldmfd r13!, {r4, r5, r6, r7}   \n"
+            "ldmfd r13!, {r4, r5, r6, r7}\n"
-        "stmfd r1!, {r4, r5, r6}    \n"
+            "stmfd r1!, {r4, r5, r6}\n"
-        "stmfd r1!, {r7}        \n"
+            "stmfd r1!, {r7}\n"
-        "stmfd r1!, {r2}        \n"
+            "stmfd r1!, {r2}\n"
-        "stmfd r1!, {r3}        \n"
+            "stmfd r1!, {r3}\n"
-        "mrs r0, spsr           \n"
+            "mrs r0, spsr\n"
-        "stmfd r1!, {r0}        \n"
+            "stmfd r1!, {r0}\n"
-        "mov r13, r1            \n"
+            "mov r13, r1\n"
-    "2:\n"
+        "2:\n"
     );
+}
 /** Returns from exception mode.
+ *
         "ldmfd sp!, {r0-r3}     \n"
     );
+}
 /** Calls exception dispatch routine. */
-#define CALL_EXC_DISPATCH(exception)        \
+#define CALL_EXC_DISPATCH(exception) \
+    asm volatile ( \
-    asm("mov r0, %0" : : "i" (exception));  \
+        "mov r0, %[exc]\n" \
-    asm("mov r1, r13");         \
+        "mov r1, r13\n" \
-    asm("bl exc_dispatch");
+        "bl exc_dispatch\n" \
+        :: [exc] "i" (exception) \
+    );\
 /** General exception handler.
+ *
  *  Stores registers, dispatches the exception,
  *  and finally restores registers and returns from exception processing.
+ *
  *  @param exception Exception number.
  */
-#define PROCESS_EXCEPTION(exception)        \
+#define PROCESS_EXCEPTION(exception) \
-    setup_stack_and_save_regs();        \
+    setup_stack_and_save_regs(); \
-    CALL_EXC_DISPATCH(exception)        \
+    CALL_EXC_DISPATCH(exception) \
     load_regs();
 /** Updates specified exception vector to jump to given handler.
+ *
  *  Addresses of handlers are stored in memory following exception vectors.
  */
-static void install_handler (unsigned handler_addr, unsigned* vector)
+static void install_handler(unsigned handler_addr, unsigned *vector)
+{
     /* relative address (related to exc. vector) of the word
      * where handler's address is stored
     */
     volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
         PREFETCH_OFFSET;
     /* make it LDR instruction and store at exception vector */
     *vector = handler_address_ptr | LDR_OPCODE;
+    smc_coherence(*vector);
     /* store handler's address */
     *(vector + EXC_VECTORS) = handler_addr;
+}
 /** Low-level Reset Exception handler. */
-static void reset_exception_entry()
+static void reset_exception_entry(void)
+{
     PROCESS_EXCEPTION(EXC_RESET);
+}
 /** Low-level Software Interrupt Exception handler. */
-static void swi_exception_entry()
+static void swi_exception_entry(void)
+{
     PROCESS_EXCEPTION(EXC_SWI);
+}
 /** Low-level Undefined Instruction Exception handler. */
-static void undef_instr_exception_entry()
+static void undef_instr_exception_entry(void)
+{
     PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
+}
 /** Low-level Fast Interrupt Exception handler. */
-static void fiq_exception_entry()
+static void fiq_exception_entry(void)
+{
     PROCESS_EXCEPTION(EXC_FIQ);
+}
 /** Low-level Prefetch Abort Exception handler. */
-static void prefetch_abort_exception_entry()
+static void prefetch_abort_exception_entry(void)
+{
     asm("sub lr, lr, #4");
     PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
+}
 /** Low-level Data Abort Exception handler. */
-static void data_abort_exception_entry()
+static void data_abort_exception_entry(void)
+{
     asm("sub lr, lr, #8");
     PROCESS_EXCEPTION(EXC_DATA_ABORT);
+}
+ *
  * CPU is switched to Undefined mode before further interrupt processing
  * because of possible occurence of nested interrupt exception, which
  * would overwrite (and thus spoil) stack pointer.
  */
-static void irq_exception_entry()
+static void irq_exception_entry(void)
+{
     asm("sub lr, lr, #4");
     setup_stack_and_save_regs();
     switch_to_irq_servicing_mode();
 /** Activates use of high exception vectors addresses. */
 static void high_vectors(void)
+{
     uint32_t control_reg;
+    asm volatile (
+        "mrc p15, 0, %[control_reg], c1, c1"
-    asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg));
+        : [control_reg] "=r" (control_reg)
+    );
     /* switch on the high vectors bit */
     control_reg |= CP15_R1_HIGH_VECTORS_BIT;
+    asm volatile (
+        "mcr p15, 0, %[control_reg], c1, c1"
-    asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
+        :: [control_reg] "r" (control_reg)
+    );
+}
 #endif
 /** Initializes exception handling.
  *
  * Installs low-level exception handlers and then registers
  * exceptions and their handlers to kernel exception dispatcher.
  */
 void exception_init(void)
+{

Subversion Repositories HelenOS

(root)/branches/dd/kernel/arch/arm32/src/exception.c – Rev 3022 → 4055