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Rev 3022 Rev 4055
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    d->offset_32_63 = offset >> 32;
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    d->offset_32_63 = offset >> 32;
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}
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}
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void tss_initialize(tss_t *t)
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void tss_initialize(tss_t *t)
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{
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{
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    memsetb((uintptr_t) t, sizeof(tss_t), 0);
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    memsetb(t, sizeof(tss_t), 0);
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}
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}
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/*
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/*
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 * This function takes care of proper setup of IDT and IDTR.
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 * This function takes care of proper setup of IDT and IDTR.
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 */
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 */
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         * ahead of page_init */
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         * ahead of page_init */
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        write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
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        write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
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        tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
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        tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
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        if (!tss_p)
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        if (!tss_p)
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            panic("could not allocate TSS\n");
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            panic("Cannot allocate TSS.");
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    }
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    }
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    tss_initialize(tss_p);
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    tss_initialize(tss_p);
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    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
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    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
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void arch_reboot(void)
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void arch_reboot(void)
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{
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{
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    preemption_disable();
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    preemption_disable();
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    ipl_t ipl = interrupts_disable();
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    ipl_t ipl = interrupts_disable();
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    memsetb((uintptr_t) idt, sizeof(idt), 0);
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    memsetb(idt, sizeof(idt), 0);
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    idtr_load(&idtr);
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    idtr_load(&idtr);
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    interrupts_restore(ipl);
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    interrupts_restore(ipl);
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    asm volatile (
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    asm volatile (
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        "int $0x03\n"
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        "int $0x03\n"