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Rev 2415 Rev 2464
Line 46... Line 46...
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void tlb_invalidate_all(void)
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void tlb_invalidate_all(void)
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{
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{
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    asm volatile (
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    asm volatile (
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        "eor r1, r1\n"
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        "eor r1, r1\n"
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        "mcr p15, 0, r1, c8, c7, 0\n"
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        "mcr p15, 0, r1, c8, c7, 0\n"
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        ::: "r1"
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        : : : "r1"
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    );
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    );
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}
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}
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-
 
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/** Invalidate all entries in TLB that belong to specified address space.
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/** Invalidate all entries in TLB that belong to specified address space.
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 *
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 *
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 * @param asid Ignored as the ARM architecture doesn't support ASIDs.
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 * @param asid Ignored as the ARM architecture doesn't support ASIDs.
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 */
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 */
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void tlb_invalidate_asid(asid_t asid)
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void tlb_invalidate_asid(asid_t asid)
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{
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{
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    tlb_invalidate_all();
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    tlb_invalidate_all();
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}
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}
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-
 
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/** Invalidate single entry in TLB
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/** Invalidate single entry in TLB
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 *
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 *
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 * @param page Virtual adress of the page
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 * @param page Virtual adress of the page
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 */
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 */
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static inline void invalidate_page(uintptr_t page)
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static inline void invalidate_page(uintptr_t page)
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{
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{
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    asm volatile (
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    asm volatile (
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        "mcr p15, 0, %0, c8, c7, 1"
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        "mcr p15, 0, %0, c8, c7, 1"    
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-
 
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        :
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        :
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        : "r"(page)
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        : "r" (page)
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    );
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    );
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}
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}
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-
 
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/** Invalidate TLB entries for specified page range belonging to specified address space.
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/** Invalidate TLB entries for specified page range belonging to specified
-
 
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 * address space.
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 *
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 *
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 * @param asid Ignored as the ARM architecture doesn't support it.
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 * @param asid Ignored as the ARM architecture doesn't support it.
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 * @param page Address of the first page whose entry is to be invalidated.
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 * @param page Address of the first page whose entry is to be invalidated.
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 * @param cnt Number of entries to invalidate.
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 * @param cnt Number of entries to invalidate.
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 */
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 */