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/*
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/*
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 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
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 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
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 * All rights reserved.
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 * All rights reserved.
4
 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
7
 * are met:
8
 *
8
 *
9
 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
14
 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup arm32mm
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/** @addtogroup arm32mm
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 * @{
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 * @{
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 */
31
 */
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/** @file
32
/** @file
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 *  @brief Page fault related functions.
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 *  @brief Page fault related functions.
34
 */
34
 */
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#include <panic.h>
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#include <panic.h>
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#include <arch/exception.h>
36
#include <arch/exception.h>
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#include <arch/debug/print.h>
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#include <arch/debug/print.h>
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#include <arch/mm/page_fault.h>
38
#include <arch/mm/page_fault.h>
39
#include <mm/as.h>
39
#include <mm/as.h>
40
#include <genarch/mm/page_pt.h>
40
#include <genarch/mm/page_pt.h>
41
#include <arch.h>
41
#include <arch.h>
42
#include <interrupt.h>
42
#include <interrupt.h>
43
 
43
 
44
 
44
/** Returns value stored in fault status register.
45
/** Returns value stored in fault status register.
45
 *
46
 *
46
 *  @return Value stored in CP15 fault status register (FSR).
47
 *  @return Value stored in CP15 fault status register (FSR).
47
 */
48
 */
48
static inline fault_status_t read_fault_status_register(void)
49
static inline fault_status_t read_fault_status_register(void)
49
{
50
{
50
    fault_status_union_t fsu;
51
    fault_status_union_t fsu;
51
 
52
 
52
    /* fault status is stored in CP15 register 5 */
53
    // fault status is stored in CP15 register 5
53
    asm volatile (
54
    asm volatile (
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        "mrc p15, 0, %0, c5, c0, 0"
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        "mrc p15, 0, %0, c5, c0, 0"
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        : "=r"(fsu.dummy)
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        : "=r"(fsu.dummy)
56
    );
57
    );
57
    return fsu.fs;
58
    return fsu.fs;
58
}
59
}
59
 
60
 
60
/** Returns FAR (fault address register) content.
61
 
61
 *
62
/** Returns FAR (fault address register) content.
62
 * @return FAR (fault address register) content (address that caused a page
63
 *
63
 *     fault)
64
 *  @return FAR (fault address register) content (address that caused a page fault)
64
 */
65
 */
65
static inline uintptr_t read_fault_address_register(void)
66
static inline uintptr_t read_fault_address_register(void)
66
{
67
{
67
    uintptr_t ret;
68
    uintptr_t ret;
68
 
69
   
69
    /* fault adress is stored in CP15 register 6 */
70
    // fault adress is stored in CP15 register 6
70
    asm volatile (
71
    asm volatile (
71
        "mrc p15, 0, %0, c6, c0, 0"
72
        "mrc p15, 0, %0, c6, c0, 0"
72
        : "=r"(ret)
73
        : "=r"(ret)
73
    );
74
    );
74
    return ret;
75
    return ret;
75
}
76
}
76
 
77
 
77
/** Decides whether the instruction is load/store or not.
78
 
78
 *
79
/** Decides whether the instruction is load/store or not.
79
 * @param instr Instruction
80
 *
80
 *
81
 * @param instr Instruction
81
 * @return true when instruction is load/store, false otherwise
82
 *
82
 */
83
 * @return true when instruction is load/store, false otherwise
83
static inline bool is_load_store_instruction(instruction_t instr)
84
 */
84
{
85
static inline bool is_load_store_instruction(instruction_t instr)
85
    /* load store immediate offset */
86
{
86
    if (instr.type == 0x2) {
87
    // load store immediate offset
87
        return true;
88
    if (instr.type == 0x2) {
88
    }
89
        return true;
89
 
90
    }
90
    /* load store register offset */
91
 
91
    if (instr.type == 0x3 && instr.bit4 == 0) {
92
    // load store register offset
92
        return true;
93
    if (instr.type == 0x3 && instr.bit4 == 0) {
93
    }
94
        return true;
94
 
95
    }
95
    /* load store multiple */
96
 
96
    if (instr.type == 0x4) {
97
    // load store multiple
97
        return true;
98
    if (instr.type == 0x4) {
98
    }
99
        return true;
99
 
100
    }
100
    /* oprocessor load/store */
101
 
101
    if (instr.type == 0x6) {
102
    // coprocessor load/store
102
        return true;
103
    if (instr.type == 0x6) {
103
    }
104
        return true;
104
 
105
    }
105
    return false;
106
 
106
}
107
    return false;
107
 
108
}
108
/** Decides whether the instruction is swap or not.
109
 
109
 *
110
 
110
 * @param instr Instruction
111
/** Decides whether the instructions is swap or not.
111
 *
112
 *
112
 * @return true when instruction is swap, false otherwise
113
 * @param instr Instruction
113
 */
114
 *
114
static inline bool is_swap_instruction(instruction_t instr)
115
 * @return true when instruction is swap, false otherwise
115
{
116
 */
116
    /* swap, swapb instruction */
117
static inline bool is_swap_instruction(instruction_t instr)
117
    if (instr.type == 0x0 &&
118
{
118
        (instr.opcode == 0x8 || instr.opcode == 0xa) &&
119
    // swap, swapb instruction
119
        instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {
120
    if (instr.type == 0x0 &&
120
        return true;
121
        (instr.opcode == 0x8 || instr.opcode == 0xa) &&
121
    }
122
        instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {
122
 
123
        return true;
123
    return false;
124
    }
124
}
125
 
125
 
126
    return false;
126
/** Decides whether read or write into memory is requested.
127
}
127
 *
128
 
128
 * @param instr_addr   Address of instruction which tries to access memory.
129
 
129
 * @param badvaddr     Virtual address the instruction tries to access.
130
/** Decides whether read or write into memory is requested.
130
 *
131
 *
131
 * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is
132
 * @param instr_addr   Address of instruction which tries to access memory.
132
 *     requested.
133
 * @param badvaddr     Virtual address the instruction tries to access.
133
 */
134
 *
134
static pf_access_t get_memory_access_type(uint32_t instr_addr,
135
 * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is requested.
135
    uintptr_t badvaddr)
136
 */
136
{
137
static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr)
137
    instruction_union_t instr_union;
138
{  
138
    instr_union.pc = instr_addr;
139
    instruction_union_t instr_union;
139
 
140
    instr_union.pc = instr_addr;
140
    instruction_t instr = *(instr_union.instr);
141
 
141
 
142
    instruction_t instr = *(instr_union.instr);
142
    /* undefined instructions */
143
 
143
    if (instr.condition == 0xf) {
144
    // undefined instructions
144
        panic("page_fault - instruction doesn't access memory "
145
    if (instr.condition == 0xf) {
145
            "(instr_code: %x, badvaddr:%x)", instr, badvaddr);
146
        panic("page_fault - instruction doesn't access memory (instr_code: %x, badvaddr:%x)",
146
        return PF_ACCESS_EXEC;
147
            instr, badvaddr);
147
    }
148
        return PF_ACCESS_EXEC;
148
 
149
    }
149
    /* load store instructions */
150
 
150
    if (is_load_store_instruction(instr)) {
151
    // load store instructions
151
        if (instr.access == 1) {
152
    if (is_load_store_instruction(instr)) {
152
            return PF_ACCESS_READ;
153
        if (instr.access == 1) {
153
        } else {
154
            return PF_ACCESS_READ;
154
            return PF_ACCESS_WRITE;
155
        } else {
155
        }
156
            return PF_ACCESS_WRITE;
156
    }
157
        }
157
 
158
    }
158
    /* swap, swpb instruction */
159
 
159
    if (is_swap_instruction(instr)) {
160
    // swap, swpb instruction
160
        return PF_ACCESS_WRITE;
161
    if (is_swap_instruction(instr)) {
161
    }
162
        return PF_ACCESS_WRITE;
162
 
163
    }
163
    panic("page_fault - instruction doesn't access memory "
164
 
164
        "(instr_code: %x, badvaddr:%x)", instr, badvaddr);
165
    panic("page_fault - instruction doesn't access memory (instr_code: %x, badvaddr:%x)",
165
 
166
        instr, badvaddr);
166
    return PF_ACCESS_EXEC;
167
 
167
}
168
    return PF_ACCESS_EXEC;
168
 
169
}
169
/** Handles "data abort" exception (load or store at invalid address).
170
 
170
 *
171
/** Handles "data abort" exception (load or store at invalid address).
171
 * @param exc_no    Exception number.
172
 *
172
 * @param istate    CPU state when exception occured.
173
 * @param exc_no    Exception number.
173
 */
174
 * @param istate    CPU state when exception occured.
174
void data_abort(int exc_no, istate_t *istate)
175
 */
175
{
176
void data_abort(int exc_no, istate_t *istate)
176
    fault_status_t fsr = read_fault_status_register();
177
{
177
    uintptr_t badvaddr = read_fault_address_register();
178
    fault_status_t fsr = read_fault_status_register();
178
 
179
    uintptr_t badvaddr = read_fault_address_register();
179
    pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
180
 
180
 
181
    pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
181
    int ret = as_page_fault(badvaddr, access, istate);
182
   
182
 
183
    int ret = as_page_fault(badvaddr, access, istate);
183
    if (ret == AS_PF_FAULT) {
184
 
184
        print_istate(istate);
185
    if (ret == AS_PF_FAULT) {
185
        dprintf("page fault - pc: %x, va: %x, status: %x(%x), "
186
        print_istate(istate);
186
            "access:%d\n", istate->pc, badvaddr, fsr.status, fsr,
187
        dprintf("page fault - pc: %x, va: %x, status: %x(%x), access:%d\n",
187
            access);
188
            istate->pc, badvaddr, fsr.status, fsr, access);
188
 
189
 
189
        fault_if_from_uspace(istate, "Page fault: %#x", badvaddr);
190
        fault_if_from_uspace(istate, "Page fault: %#x", badvaddr);
190
        panic("page fault\n");
191
        panic("page fault\n");
191
    }
192
    }
192
}
193
}
193
 
194
 
194
/** Handles "prefetch abort" exception (instruction couldn't be executed).
195
/** Handles "prefetch abort" exception (instruction couldn't be executed).
195
 *
196
 *
196
 * @param exc_no    Exception number.
197
 * @param exc_no    Exception number.
197
 * @param istate    CPU state when exception occured.
198
 * @param istate    CPU state when exception occured.
198
 */
199
 */
199
void prefetch_abort(int exc_no, istate_t *istate)
200
void prefetch_abort(int exc_no, istate_t *istate)
200
{
201
{
201
    int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
202
    int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
202
 
203
 
203
    if (ret == AS_PF_FAULT) {
204
    if (ret == AS_PF_FAULT) {
204
        dprintf("prefetch_abort\n");
205
        dprintf("prefetch_abort\n");
205
        print_istate(istate);
206
        print_istate(istate);
206
        panic("page fault - prefetch_abort at address: %x\n",
207
        panic("page fault - prefetch_abort at address: %x\n", istate->pc);
207
            istate->pc);
208
    }
208
    }
209
}
209
}
210
 
210
 
211
/** @}
211
/** @}
212
 */
212
 */
213
 
-