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| Rev 2274 | Rev 2312 | ||
|---|---|---|---|
| Line 47... | Line 47... | ||
| 47 | */ |
47 | */ |
| 48 | ipl_t interrupts_disable(void) |
48 | ipl_t interrupts_disable(void) |
| 49 | { |
49 | { |
| 50 | ipl_t ipl = current_status_reg_read(); |
50 | ipl_t ipl = current_status_reg_read(); |
| 51 | 51 | ||
| 52 | current_status_reg_control_write(ipl & ~STATUS_REG_IE_ENABLED_BIT); |
52 | current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl); |
| 53 | 53 | ||
| 54 | return ipl; |
54 | return ipl; |
| 55 | } |
55 | } |
| 56 | 56 | ||
| 57 | /** Enable interrupts. |
57 | /** Enable interrupts. |
| Line 60... | Line 60... | ||
| 60 | */ |
60 | */ |
| 61 | ipl_t interrupts_enable(void) |
61 | ipl_t interrupts_enable(void) |
| 62 | { |
62 | { |
| 63 | ipl_t ipl = current_status_reg_read(); |
63 | ipl_t ipl = current_status_reg_read(); |
| 64 | 64 | ||
| 65 | current_status_reg_control_write(ipl | STATUS_REG_IE_ENABLED_BIT); |
65 | current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT); |
| 66 | 66 | ||
| 67 | return ipl; |
67 | return ipl; |
| 68 | } |
68 | } |
| 69 | 69 | ||
| 70 | /** Restore interrupt priority level. |
70 | /** Restore interrupt priority level. |
| Line 72... | Line 72... | ||
| 72 | * @param ipl Saved interrupt priority level. |
72 | * @param ipl Saved interrupt priority level. |
| 73 | */ |
73 | */ |
| 74 | void interrupts_restore(ipl_t ipl) |
74 | void interrupts_restore(ipl_t ipl) |
| 75 | { |
75 | { |
| 76 | current_status_reg_control_write(current_status_reg_read() | |
76 | current_status_reg_control_write(current_status_reg_read() | |
| 77 | (ipl & STATUS_REG_IE_ENABLED_BIT)); |
77 | (ipl & STATUS_REG_IRQ_DISABLED_BIT)); |
| 78 | } |
78 | } |
| 79 | 79 | ||
| 80 | /** Read interrupt priority level. |
80 | /** Read interrupt priority level. |
| 81 | * |
81 | * |
| 82 | * @return Current interrupt priority level. |
82 | * @return Current interrupt priority level. |