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| 40 | #include <interrupt.h> |
40 | #include <interrupt.h> |
| 41 | 41 | ||
| 42 | /** Initial size of a table holding interrupt handlers. */ |
42 | /** Initial size of a table holding interrupt handlers. */ |
| 43 | #define IRQ_COUNT 8 |
43 | #define IRQ_COUNT 8 |
| 44 | 44 | ||
| 45 | - | ||
| 46 | /** Disable interrupts. |
45 | /** Disable interrupts. |
| 47 | * |
46 | * |
| 48 | * @return Old interrupt priority level. |
47 | * @return Old interrupt priority level. |
| 49 | */ |
48 | */ |
| 50 | ipl_t interrupts_disable(void) |
49 | ipl_t interrupts_disable(void) |
| Line 54... | Line 53... | ||
| 54 | current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl); |
53 | current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl); |
| 55 | 54 | ||
| 56 | return ipl; |
55 | return ipl; |
| 57 | } |
56 | } |
| 58 | 57 | ||
| 59 | - | ||
| 60 | /** Enable interrupts. |
58 | /** Enable interrupts. |
| 61 | * |
59 | * |
| 62 | * @return Old interrupt priority level. |
60 | * @return Old interrupt priority level. |
| 63 | */ |
61 | */ |
| 64 | ipl_t interrupts_enable(void) |
62 | ipl_t interrupts_enable(void) |
| Line 68... | Line 66... | ||
| 68 | current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT); |
66 | current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT); |
| 69 | 67 | ||
| 70 | return ipl; |
68 | return ipl; |
| 71 | } |
69 | } |
| 72 | 70 | ||
| 73 | - | ||
| 74 | /** Restore interrupt priority level. |
71 | /** Restore interrupt priority level. |
| 75 | * |
72 | * |
| 76 | * @param ipl Saved interrupt priority level. |
73 | * @param ipl Saved interrupt priority level. |
| 77 | */ |
74 | */ |
| 78 | void interrupts_restore(ipl_t ipl) |
75 | void interrupts_restore(ipl_t ipl) |
| 79 | { |
76 | { |
| 80 | current_status_reg_control_write( |
77 | current_status_reg_control_write( |
| 81 | (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) | |
78 | (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) | |
| 82 | (ipl & STATUS_REG_IRQ_DISABLED_BIT) |
79 | (ipl & STATUS_REG_IRQ_DISABLED_BIT)); |
| 83 | ); |
- | |
| 84 | } |
80 | } |
| 85 | 81 | ||
| 86 | - | ||
| 87 | /** Read interrupt priority level. |
82 | /** Read interrupt priority level. |
| 88 | * |
83 | * |
| 89 | * @return Current interrupt priority level. |
84 | * @return Current interrupt priority level. |
| 90 | */ |
85 | */ |
| 91 | ipl_t interrupts_read(void) |
86 | ipl_t interrupts_read(void) |
| 92 | { |
87 | { |
| 93 | return current_status_reg_read(); |
88 | return current_status_reg_read(); |
| 94 | } |
89 | } |
| 95 | 90 | ||
| 96 | - | ||
| 97 | /** Initialize basic tables for exception dispatching |
91 | /** Initialize basic tables for exception dispatching |
| 98 | * and starts the timer. |
92 | * and starts the timer. |
| 99 | */ |
93 | */ |
| 100 | void interrupt_init(void) |
94 | void interrupt_init(void) |
| 101 | { |
95 | { |
| 102 | irq_init(IRQ_COUNT, IRQ_COUNT); |
96 | irq_init(IRQ_COUNT, IRQ_COUNT); |
| 103 | machine_timer_irq_start(); |
97 | machine_timer_irq_start(); |
| 104 | } |
98 | } |
| 105 | 99 | ||
| 106 | - | ||
| 107 | /** @} |
100 | /** @} |
| 108 | */ |
101 | */ |