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    unsigned domain              : 4;
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    unsigned domain              : 4;
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    unsigned should_be_zero_1    : 1;
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    unsigned should_be_zero_1    : 1;
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    unsigned access_permission   : 2;  
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    unsigned access_permission   : 2;  
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    unsigned should_be_zero_2    : 8;
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    unsigned should_be_zero_2    : 8;
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    unsigned section_base_addr   : 12;
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    unsigned section_base_addr   : 12;
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} __attribute__ ((packed)) pte_level0_section;
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} __attribute__ ((packed)) pte_level0_section_t;
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/** Page table that holds 1:1 mapping for booting the kernel. */
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/** Page table that holds 1:1 mapping for booting the kernel. */
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extern pte_level0_section page_table[PTL0_ENTRIES_ARCH];
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extern pte_level0_section_t page_table[PTL0_ENTRIES_ARCH];
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/** Starts the MMU - initializes page table and enables paging. */
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/** Starts the MMU - initializes page table and enables paging. */
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void mmu_start(void);
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void mmu_start(void);
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/** Sets the address of level 0 page table.
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/** Sets the address of level 0 page table.
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 * \param pt pointer to the page table to set
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 * \param pt pointer to the page table to set
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 */  
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 */  
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static inline void set_ptl0_address(pte_level0_section* pt)
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static inline void set_ptl0_address(pte_level0_section_t* pt)
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{
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{
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    asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
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    asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
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        :
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        :
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        : "r"(pt)
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        : "r"(pt)
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    );
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    );
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}
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}
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#endif
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#endif