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/** @file
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/** @file
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 */
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 */
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#include "mm.h"
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#include "mm.h"
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/** Initializes section page table entry.
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/** Initializes section page table entry.
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 *
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 *
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 *  Will be readable/writable by kernel with no access from user mode.
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 *  Will be readable/writable by kernel with no access from user mode.
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 *  Will belong to domain 0. No cache or buffering is enabled.
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 *  Will belong to domain 0. No cache or buffering is enabled.
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 *  
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 *  
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 *  \param pte    page table entry to set
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 *  \param pte    page table entry to set
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 *  \param frame  first frame in the section (frame number)
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 *  \param frame  first frame in the section (frame number)
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 *  \note  If frame is not 1MB aligned, first lower 1MB aligned frame will be used.
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 *  \note  If frame is not 1MB aligned, first lower 1MB aligned frame will be used.
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 */  
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 */  
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static void init_pte_level0_section(pte_level0_section* pte, unsigned frame){
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static void init_pte_level0_section(pte_level0_section* pte, unsigned frame)
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{
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    pte->descriptor_type   = PTE_DESCRIPTOR_SECTION;
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    pte->descriptor_type   = PTE_DESCRIPTOR_SECTION;
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    pte->bufferable        = 0; // disable
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    pte->bufferable        = 0;
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    pte->cacheable         = 0;
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    pte->cacheable         = 0;
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    pte->impl_specific     = 0;
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    pte->impl_specific     = 0;
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    pte->domain            = 0;
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    pte->domain            = 0;
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    pte->should_be_zero_1  = 0;
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    pte->should_be_zero_1  = 0;
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    pte->access_permission = PTE_AP_USER_NO_KERNEL_RW; 
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    pte->access_permission = PTE_AP_USER_NO_KERNEL_RW; 
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    pte->should_be_zero_2  = 0;
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    pte->should_be_zero_2  = 0;
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    pte->section_base_addr = (frame << FRAME_WIDTH) >> 20;
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    pte->section_base_addr = (frame << FRAME_WIDTH) >> 20;
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};
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}
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void mm_kernel_mapping(void) {
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static void init_page_table(void)
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{
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    int i;
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    int i;
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    const unsigned int first_kernel_section = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION;
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    const unsigned int first_kernel_section = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION;
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    // create 1:1 mapping (in lower 2GB)
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    // create 1:1 mapping virtual-physical (in lower 2GB)
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    for(i = 0; i < first_kernel_section; i++) {
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    for(i = 0; i < first_kernel_section; i++) {
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        init_pte_level0_section(&page_table[i], i * FRAMES_PER_SECTION);
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        init_pte_level0_section(&page_table[i], i * FRAMES_PER_SECTION);
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    }
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    }
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    // create kernel mapping (in upper 2GB), physical addresses starting from 0
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    // create kernel mapping (in upper 2GB), physical addresses starting from 0
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    for(i = first_kernel_section; i < PTL0_ENTRIES_ARCH; i++) {
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    for(i = first_kernel_section; i < PTL0_ENTRIES_ARCH; i++) {
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        init_pte_level0_section(&page_table[i], (i - first_kernel_section) * FRAMES_PER_SECTION);
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        init_pte_level0_section(&page_table[i], (i - first_kernel_section) * FRAMES_PER_SECTION);
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    }
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    }
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}
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void mmu_start() {
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    init_page_table();
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    set_ptl0_address(page_table);
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    set_ptl0_address(page_table);
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    // enable paging
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    enable_paging();
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    asm volatile (
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        "ldr r0, =0x55555555       \n"
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        "mcr p15, 0, r0, c3, c0, 0 \n" // TODO: comment: set domain access rights to client <==> take rights from page tables
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        "mrc p15, 0, r0, c1, c0, 0 \n" // get current settings of system
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        "ldr r1, =0xFFFFFE8D       \n" // mask to disable aligment checks; system & rom bit disabled
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        "and r0, r0, r1            \n"
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        "ldr r1, =0x00000001       \n" // mask to enable paging
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        "orr r0, r0, r1            \n"
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        "mcr p15, 0, r0, c1, c0, 0 \n" // store settings
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        :
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        :
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        : "r0", "r1"
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    );
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};
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}
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/** @}
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/** @}
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 */
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 */
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