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 */
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 */
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/** @file
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/** @file
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 */
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 */
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#include "mm.h"
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#include "mm.h"
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/** Set page table entry to point no frame, be read/write by kernel,
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 *   no access by user, become to domain 0, no cache or buffer
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 *   \param pte page table entry to set
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 *   \param frame frame number of first frame 1MB section
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 *   Note: If frame not aligned it's used first lower  1MB aligned frame
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 */  
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void init_pte_level0_section_entry( pte_level0_section* pte, unsigned frame){
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static void init_pte_level0_section_entry( pte_level0_section* pte, unsigned frame){
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    pte->descriptor_type   = pte_descriptor_section;
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    pte->descriptor_type   = PTE_DESCRIPTOR_SECTION;
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    pte->bufferable        = 0; // disable
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    pte->bufferable        = 0; // disable
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    pte->cacheable         = 0;
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    pte->cacheable         = 0;
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    pte->machine_depend    = 0;
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    pte->machine_depend    = 0;
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    pte->domain            = 0;
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    pte->domain            = 0;
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    pte->should_be_zero_1  = 0;
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    pte->should_be_zero_1  = 0;
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    pte->access_permission =  pte_ap_user_no_kernel_rw;
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    pte->access_permission = PTE_AP_USER_NO_KERNEL_RW; 
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    pte->should_be_zero_2  = 0;
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    pte->should_be_zero_2  = 0;
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    pte->section_base_addr = (frame << FRAME_WIDTH) >> 20;
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    pte->section_base_addr = (frame << FRAME_WIDTH) >> 20;
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};
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};
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// set memory mapping for kernel
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void mm_kernel_mapping(void) {
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void mm_kernel_mapping(void) {
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    int i;
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    int i;
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    // Create 1:1 mapping
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    // Create 1:1 mapping
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    for( i=0; i < 4096; i++)
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    for( i=0; i < PTL0_ENTRIES_ARCH; i++) {
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        init_pte_level0_section_entry(&page_table[i+0000], i * FRAMES_PER_SECTION);
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        init_pte_level0_section_entry(&page_table[i], i * FRAMES_PER_SECTION);
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    }
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    // Create Kernel mapping
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    // Create kernel mapping
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    const unsigned int offset = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION;
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    const unsigned int offset = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION;
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    for( i = offset; i < 4096; i++)
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    for( i = offset; i < PTL0_ENTRIES_ARCH; i++) {
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        init_pte_level0_section_entry(&page_table[i], (i - offset) * FRAMES_PER_SECTION);
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        init_pte_level0_section_entry(&page_table[i], (i - offset) * FRAMES_PER_SECTION);
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    }
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    SET_PTL0_ADDRESS_ARCH( page_table);
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    SET_PTL0_ADDRESS_ARCH( page_table);
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    // enable paging
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    // Enable paging
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    asm volatile (
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    asm volatile (
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        "ldr r0, =0x55555555       \n"
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    "ldr r0, =0x55555555       \n"
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        "mcr p15, 0, r0, c3, c0, 0 \n" //set domain acces rights to client <==> take rights from page tables
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    "mcr p15, 0, r0, c3, c0, 0 \n" // Set domain acces rights to client <==> take rights from page tables
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        "mrc p15, 0, r0, c1, c0, 0 \n" // get current setting of system ... register 1 isn't only for memmory management
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    "mrc p15, 0, r0, c1, c0, 0 \n" // Get current setting of system ... register 1 isn't only for memmory management
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        "ldr r1, =0xFFFFFE8D       \n" // mask to disable aligment checks, System, Rom bit disable
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    "ldr r1, =0xFFFFFE8D       \n" // Mask to disable aligment checks; system & rom bit disable
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        "and r0, r0, r1            \n"
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    "and r0, r0, r1            \n"
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        "ldr r1, =0x00000001       \n" // mask to enable paging
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    "ldr r1, =0x00000001       \n" // Mask to enable paging
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        "orr r0, r0, r1            \n"
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    "orr r0, r0, r1            \n"
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        "mcr p15, 0, r0, c1, c0, 0 \n" // store setting
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    "mcr p15, 0, r0, c1, c0, 0 \n" // Store setting
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        :
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    :
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        :
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    :
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        : "r0", "r1"
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    : "r0", "r1"
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    );
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    );
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};
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};
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/** @}
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/** @}
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 */
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 */
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