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27 | # |
27 | # |
28 | 28 | ||
29 | #include "regname.h" |
29 | #include "regname.h" |
30 | #include "spr.h" |
30 | #include "spr.h" |
31 | 31 | ||
- | 32 | .data |
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- | 33 | ||
- | 34 | flush_buffer: |
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- | 35 | .space 4 |
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- | 36 | ||
32 | .text |
37 | .text |
33 | 38 | ||
34 | .global memsetb |
39 | .global memsetb |
35 | .global memcpy |
40 | .global memcpy |
36 | .global halt |
41 | .global halt |
Line 142... | Line 147... | ||
142 | b 1b |
147 | b 1b |
143 | 148 | ||
144 | halt: |
149 | halt: |
145 | b halt |
150 | b halt |
146 | 151 | ||
- | 152 | flush_instruction_cache: |
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- | 153 | ||
- | 154 | # Flush data cache |
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- | 155 | ||
- | 156 | lis r3, flush_buffer@h |
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- | 157 | ori r3, r3, flush_buffer@l |
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- | 158 | li r4, L1_CACHE_LINES |
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- | 159 | mtctr r4 |
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- | 160 | ||
- | 161 | 0: |
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- | 162 | ||
- | 163 | lwz r4, 0(r3) |
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- | 164 | addi r3, r3, L1_CACHE_BYTES |
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- | 165 | bdnz 0b |
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- | 166 | ||
- | 167 | # Invalidate instruction cache |
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- | 168 | ||
- | 169 | li r3, 0 |
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- | 170 | ori r3, r3, (HID0_ICE | HID0_DCE | HID0_ICFI | HID0_DCI) |
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- | 171 | mfspr r4, SPRN_HID0 |
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- | 172 | or r5, r4, r3 |
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- | 173 | isync |
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- | 174 | mtspr SPRN_HID0, r5 |
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- | 175 | sync |
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- | 176 | isync |
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- | 177 | ||
- | 178 | # Enable instruction cache |
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- | 179 | ||
- | 180 | ori r5, r4, HID0_ICE |
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- | 181 | mtspr SPRN_HID0, r5 |
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- | 182 | sync |
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- | 183 | isync |
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- | 184 | blr |
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- | 185 | ||
147 | jump_to_kernel: |
186 | jump_to_kernel: |
148 | mfmsr r4 |
187 | mfmsr r4 |
149 | andis. r4, r4, (~MSR_DR | MSR_IR) >> 16 |
188 | andis. r4, r4, (~MSR_DR | MSR_IR) >> 16 |
150 | mtspr SPRN_SRR0, r3 |
189 | mtspr SPRN_SRR0, r3 |
151 | mtspr SPRN_SRR1, r4 |
190 | mtspr SPRN_SRR1, r4 |
152 | sync |
191 | bl flush_instruction_cache |
153 | RFI |
192 | rfi |