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| Rev 964 | Rev 1003 | ||
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| Line 25... | Line 25... | ||
| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | # |
27 | # |
| 28 | 28 | ||
| 29 | #include "regname.h" |
29 | #include "regname.h" |
| 30 | #include "spr.h" |
- | |
| 31 | 30 | ||
| 32 | .data |
31 | .data |
| 33 | 32 | ||
| 34 | flush_buffer: |
33 | flush_buffer: |
| 35 | .space (L1_CACHE_LINES * L1_CACHE_BYTES) |
34 | .space (L1_CACHE_LINES * L1_CACHE_BYTES) |
| Line 162... | Line 161... | ||
| 162 | bdnz 0b |
161 | bdnz 0b |
| 163 | 162 | ||
| 164 | # Invalidate instruction cache |
163 | # Invalidate instruction cache |
| 165 | 164 | ||
| 166 | li r3, 0 |
165 | li r3, 0 |
| 167 | ori r3, r3, (HID0_ICE | HID0_DCE | HID0_ICFI | HID0_DCI) |
166 | ori r3, r3, (hid0_ice | hid0_dce | hid0_icfi | hid0_dci) |
| 168 | mfspr r4, SPRN_HID0 |
167 | mfspr r4, hid0 |
| 169 | or r5, r4, r3 |
168 | or r5, r4, r3 |
| 170 | isync |
169 | isync |
| 171 | mtspr SPRN_HID0, r5 |
170 | mtspr hid0, r5 |
| 172 | sync |
171 | sync |
| 173 | isync |
172 | isync |
| 174 | 173 | ||
| 175 | # Enable instruction cache |
174 | # Enable instruction cache |
| 176 | 175 | ||
| 177 | ori r5, r4, HID0_ICE |
176 | ori r5, r4, hid0_ice |
| 178 | mtspr SPRN_HID0, r5 |
177 | mtspr hid0, r5 |
| 179 | sync |
178 | sync |
| 180 | isync |
179 | isync |
| 181 | blr |
180 | blr |
| 182 | 181 | ||
| 183 | jump_to_kernel: |
182 | jump_to_kernel: |
| 184 | mr r10, r4 |
183 | mr r10, r4 |
| 185 | mtlr r3 |
184 | mtlr r3 |
| 186 | blr |
185 | blr |
| 187 | - | ||