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34 | { |
34 | { |
35 | register sysarg_t __mips_reg_a0 asm("$4") = p1; |
35 | register sysarg_t __mips_reg_a0 asm("$4") = p1; |
36 | register sysarg_t __mips_reg_a1 asm("$5") = p2; |
36 | register sysarg_t __mips_reg_a1 asm("$5") = p2; |
37 | register sysarg_t __mips_reg_a2 asm("$6") = p3; |
37 | register sysarg_t __mips_reg_a2 asm("$6") = p3; |
38 | register sysarg_t __mips_reg_a3 asm("$7") = p4; |
38 | register sysarg_t __mips_reg_a3 asm("$7") = p4; |
39 | register sysarg_t __mips_reg_t0 asm("$8") = id; |
39 | register sysarg_t __mips_reg_v0 asm("$2") = id; |
40 | register sysarg_t __mips_reg_v0 asm("$2"); |
- | |
41 | 40 | ||
42 | asm volatile ( |
41 | asm volatile ( |
43 | "syscall\n" |
42 | "syscall\n" |
44 | : "=r" (__mips_reg_v0) |
43 | : "=r" (__mips_reg_v0) |
45 | : "r" (__mips_reg_a0), |
44 | : "r" (__mips_reg_a0), |
46 | "r" (__mips_reg_a1), |
45 | "r" (__mips_reg_a1), |
47 | "r" (__mips_reg_a2), |
46 | "r" (__mips_reg_a2), |
48 | "r" (__mips_reg_a3), |
47 | "r" (__mips_reg_a3), |
49 | "r" (__mips_reg_t0) |
48 | "r" (__mips_reg_v0) |
50 | ); |
49 | ); |
51 | 50 | ||
52 | return __mips_reg_v0; |
51 | return __mips_reg_v0; |
53 | } |
52 | } |