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Line 768... | Line 768... | ||
768 | */ |
768 | */ |
769 | 769 | ||
770 | void fat_mounted(ipc_callid_t rid, ipc_call_t *request) |
770 | void fat_mounted(ipc_callid_t rid, ipc_call_t *request) |
771 | { |
771 | { |
772 | dev_handle_t dev_handle = (dev_handle_t) IPC_GET_ARG1(*request); |
772 | dev_handle_t dev_handle = (dev_handle_t) IPC_GET_ARG1(*request); |
- | 773 | enum cache_mode cmode; |
|
773 | fat_bs_t *bs; |
774 | fat_bs_t *bs; |
774 | uint16_t bps; |
775 | uint16_t bps; |
775 | uint16_t rde; |
776 | uint16_t rde; |
776 | int rc; |
777 | int rc; |
777 | 778 | ||
Line 795... | Line 796... | ||
795 | free(opts); |
796 | free(opts); |
796 | return; |
797 | return; |
797 | } |
798 | } |
798 | opts[size] = '\0'; |
799 | opts[size] = '\0'; |
799 | 800 | ||
- | 801 | /* Check for option enabling write through. */ |
|
- | 802 | if (str_cmp(opts, "wtcache") == 0) |
|
- | 803 | cmode = CACHE_MODE_WT; |
|
- | 804 | else |
|
- | 805 | cmode = CACHE_MODE_WB; |
|
- | 806 | ||
800 | /* initialize libblock */ |
807 | /* initialize libblock */ |
801 | rc = block_init(dev_handle, BS_SIZE); |
808 | rc = block_init(dev_handle, BS_SIZE); |
802 | if (rc != EOK) { |
809 | if (rc != EOK) { |
803 | ipc_answer_0(rid, rc); |
810 | ipc_answer_0(rid, rc); |
804 | return; |
811 | return; |
Line 824... | Line 831... | ||
824 | ipc_answer_0(rid, ENOTSUP); |
831 | ipc_answer_0(rid, ENOTSUP); |
825 | return; |
832 | return; |
826 | } |
833 | } |
827 | 834 | ||
828 | /* Initialize the block cache */ |
835 | /* Initialize the block cache */ |
829 | rc = block_cache_init(dev_handle, bps, 0 /* XXX */); |
836 | rc = block_cache_init(dev_handle, bps, 0 /* XXX */, cmode); |
830 | if (rc != EOK) { |
837 | if (rc != EOK) { |
831 | block_fini(dev_handle); |
838 | block_fini(dev_handle); |
832 | ipc_answer_0(rid, rc); |
839 | ipc_answer_0(rid, rc); |
833 | return; |
840 | return; |
834 | } |
841 | } |