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Rev 4251 | Rev 4311 | ||
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Line 42... | Line 42... | ||
42 | #include <arch/asm.h> |
42 | #include <arch/asm.h> |
43 | #include <console/chardev.h> |
43 | #include <console/chardev.h> |
44 | #include <mm/slab.h> |
44 | #include <mm/slab.h> |
45 | #include <ddi/device.h> |
45 | #include <ddi/device.h> |
46 | 46 | ||
47 | static indev_operations_t kbrdin_ops = { |
- | |
48 | .poll = NULL |
- | |
49 | }; |
- | |
50 | - | ||
51 | #define i8042_SET_COMMAND 0x60 |
47 | #define i8042_SET_COMMAND 0x60 |
52 | #define i8042_COMMAND 0x69 |
48 | #define i8042_COMMAND 0x69 |
53 | #define i8042_CPU_RESET 0xfe |
49 | #define i8042_CPU_RESET 0xfe |
54 | 50 | ||
55 | #define i8042_BUFFER_FULL_MASK 0x01 |
51 | #define i8042_BUFFER_FULL_MASK 0x01 |
Line 72... | Line 68... | ||
72 | i8042_t *dev = instance->i8042; |
68 | i8042_t *dev = instance->i8042; |
73 | uint8_t status; |
69 | uint8_t status; |
74 | 70 | ||
75 | if (((status = pio_read_8(&dev->status)) & i8042_BUFFER_FULL_MASK)) { |
71 | if (((status = pio_read_8(&dev->status)) & i8042_BUFFER_FULL_MASK)) { |
76 | uint8_t data = pio_read_8(&dev->data); |
72 | uint8_t data = pio_read_8(&dev->data); |
77 | indev_push_character(&instance->kbrdin, data); |
73 | indev_push_character(instance->kbrdin, data); |
78 | } |
74 | } |
79 | } |
75 | } |
80 | 76 | ||
- | 77 | /**< Clear input buffer. */ |
|
- | 78 | static void i8042_clear_buffer(i8042_t *dev) |
|
- | 79 | { |
|
- | 80 | while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK) |
|
- | 81 | (void) pio_read_8(&dev->data); |
|
- | 82 | } |
|
- | 83 | ||
81 | /** Initialize i8042. */ |
84 | /** Initialize i8042. */ |
82 | indev_t *i8042_init(i8042_t *dev, inr_t inr) |
85 | i8042_instance_t *i8042_init(i8042_t *dev, inr_t inr) |
83 | { |
86 | { |
84 | i8042_instance_t *instance |
87 | i8042_instance_t *instance |
85 | = malloc(sizeof(i8042_instance_t), FRAME_ATOMIC); |
88 | = malloc(sizeof(i8042_instance_t), FRAME_ATOMIC); |
86 | if (!instance) |
89 | if (instance) { |
- | 90 | instance->i8042 = dev; |
|
87 | return NULL; |
91 | instance->kbrdin = NULL; |
88 | 92 | ||
89 | indev_initialize("i8042", &instance->kbrdin, &kbrdin_ops); |
93 | irq_initialize(&instance->irq); |
- | 94 | instance->irq.devno = device_assign_devno(); |
|
- | 95 | instance->irq.inr = inr; |
|
- | 96 | instance->irq.claim = i8042_claim; |
|
- | 97 | instance->irq.handler = i8042_irq_handler; |
|
- | 98 | instance->irq.instance = instance; |
|
- | 99 | ||
- | 100 | } |
|
90 | 101 | ||
91 | instance->i8042 = dev; |
102 | return instance; |
- | 103 | } |
|
- | 104 | ||
- | 105 | void i8042_wire(i8042_instance_t *instance, indev_t *kbrdin) |
|
- | 106 | { |
|
- | 107 | ASSERT(instance); |
|
- | 108 | ASSERT(kbrdin); |
|
92 | 109 | ||
93 | irq_initialize(&instance->irq); |
- | |
94 | instance->irq.devno = device_assign_devno(); |
- | |
95 | instance->irq.inr = inr; |
110 | instance->kbrdin = kbrdin; |
96 | instance->irq.claim = i8042_claim; |
- | |
97 | instance->irq.handler = i8042_irq_handler; |
- | |
98 | instance->irq.instance = instance; |
- | |
99 | irq_register(&instance->irq); |
111 | irq_register(&instance->irq); |
100 | - | ||
101 | /* Clear input buffer */ |
- | |
102 | while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK) |
- | |
103 | (void) pio_read_8(&dev->data); |
- | |
104 | - | ||
105 | return &instance->kbrdin; |
112 | i8042_clear_buffer(instance->i8042); |
106 | } |
113 | } |
107 | 114 | ||
108 | /* Reset CPU by pulsing pin 0 */ |
115 | /* Reset CPU by pulsing pin 0 */ |
109 | void i8042_cpu_reset(i8042_t *dev) |
116 | void i8042_cpu_reset(i8042_t *dev) |
110 | { |
117 | { |
111 | interrupts_disable(); |
118 | interrupts_disable(); |
112 | 119 | ||
113 | /* Clear input buffer */ |
120 | i8042_clear_buffer(dev); |
114 | while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK) |
- | |
115 | (void) pio_read_8(&dev->data); |
- | |
116 | 121 | ||
117 | /* Reset CPU */ |
122 | /* Reset CPU */ |
118 | pio_write_8(&dev->status, i8042_CPU_RESET); |
123 | pio_write_8(&dev->status, i8042_CPU_RESET); |
119 | } |
124 | } |
120 | 125 |