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Rev 4223 Rev 4251
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    .poll = NULL
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    .poll = NULL
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};
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};
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#define i8042_SET_COMMAND  0x60
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#define i8042_SET_COMMAND  0x60
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#define i8042_COMMAND      0x69
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#define i8042_COMMAND      0x69
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#define i8042_CPU_RESET    0xfe
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#define i8042_BUFFER_FULL_MASK  0x01
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#define i8042_BUFFER_FULL_MASK  0x01
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#define i8042_WAIT_MASK         0x02
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#define i8042_WAIT_MASK         0x02
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static irq_ownership_t i8042_claim(irq_t *irq)
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static irq_ownership_t i8042_claim(irq_t *irq)
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    instance->irq.claim = i8042_claim;
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    instance->irq.claim = i8042_claim;
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    instance->irq.handler = i8042_irq_handler;
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    instance->irq.handler = i8042_irq_handler;
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    instance->irq.instance = instance;
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    instance->irq.instance = instance;
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    irq_register(&instance->irq);
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    irq_register(&instance->irq);
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    /*
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     * Clear input buffer.
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    /* Clear input buffer */
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     */
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    while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK)
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    while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK)
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        (void) pio_read_8(&dev->data);
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        (void) pio_read_8(&dev->data);
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    return &instance->kbrdin;
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    return &instance->kbrdin;
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}
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}
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- 
 
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/* Reset CPU by pulsing pin 0 */
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void i8042_cpu_reset(i8042_t *dev)
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{
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    interrupts_disable();
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    /* Clear input buffer */
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    while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK)
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        (void) pio_read_8(&dev->data);
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    /* Reset CPU */
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    pio_write_8(&dev->status, i8042_CPU_RESET);
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}
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/** @}
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/** @}
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 */
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 */