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/** Take over TLB and trap table.

 *

 * Initialize ITLB and DTLB and switch to kernel

 * trap table.

 *

 * First, demap context 0 and install the

 * global 4M locked kernel mapping.

 *

 * Second, prepare a temporary IMMU mapping in

 * context 1, switch to it, demap context 0,

 * install the global 4M locked kernel mapping

 * in context 0 and switch back to context 0.

 *

 * @param base Base address that will be hardwired in both TLBs.

 */

void take_over_tlb_and_tt(uintptr_t base)

{

    tlb_tag_access_reg_t tag;

    tlb_data_t data;

    frame_address_t fr;

    page_address_t pg;

    /*

     * Switch to the kernel trap table.

     */

    trap_switch_trap_table();

    fr.address = base;

    pg.address = base;

    /*

     * We do identity mapping of 4M-page at 4M.

     */

    tag.value = 0;

    tag.context = 0;

    tag.vpn = pg.vpn;

    data.value = 0;

    data.v = true;

    data.size = PAGESIZE_4M;

    data.pfn = fr.pfn;

    data.l = true;

    data.cp = 1;

    data.cv = 0;

    data.p = true;

    data.w = true;

    data.g = true;

    /*

     * Straightforwardly demap DMUU context 0,

     * and replace it with the locked kernel mapping.

     */

    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);

    dtlb_tag_access_write(tag.value);

    dtlb_data_in_write(data.value);

    /*

     * Install kernel code mapping in context 1

     * and switch to it.

     */

    tag.context = 1;

    data.g = false;

    itlb_tag_access_write(tag.value);

    itlb_data_in_write(data.value);

    mmu_primary_context_write(1);

    /*

     * Demap old context 0.

     */

    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);

    /*

     * Install the locked kernel mapping in context 0

     * and switch to it.

     */

    tag.context = 0;

    data.g = true;

    itlb_tag_access_write(tag.value);

    itlb_data_in_write(data.value);

    mmu_primary_context_write(0);

}