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/** Take over TLB and trap table.
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/** Take over TLB and trap table.
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 *
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 *
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 * Initialize ITLB and DTLB and switch to kernel
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 * Initialize ITLB and DTLB and switch to kernel
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 * trap table.
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 * trap table.
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 *
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 *
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 * The goal of this function is to disable MMU
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 * First, demap context 0 and install the
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 * so that both TLBs can be purged and new
 - 
 
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 * kernel 4M locked entry can be installed.
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 * global 4M locked kernel mapping.
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 * After TLB is initialized, MMU is enabled
 - 
 
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 * again.
 - 
 
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 *
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 *
- 
 
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 * Second, prepare a temporary IMMU mapping in
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 * Switching MMU off imposes the requirement for
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 * context 1, switch to it, demap context 0,
- 
 
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 * install the global 4M locked kernel mapping
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 * the kernel to run in identity mapped environment.
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 * in context 0 and switch back to context 0.
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 *
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 *
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 * @param base Base address that will be hardwired in both TLBs.
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 * @param base Base address that will be hardwired in both TLBs.
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 */
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 */
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void take_over_tlb_and_tt(uintptr_t base)
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void take_over_tlb_and_tt(uintptr_t base)
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{
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{
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    tlb_tag_access_reg_t tag;
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    tlb_tag_access_reg_t tag;
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    tlb_data_t data;
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    tlb_data_t data;
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    frame_address_t fr;
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    frame_address_t fr;
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    page_address_t pg;
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    page_address_t pg;
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- 
 
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    /*
- 
 
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     * Switch to the kernel trap table.
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     */
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    trap_switch_trap_table();
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    fr.address = base;
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    fr.address = base;
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    pg.address = base;
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    pg.address = base;
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    immu_disable();
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    dmmu_disable();
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 - 
 
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    /*
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     * Demap everything, especially OpenFirmware.
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     */
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    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
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    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
 - 
 
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 - 
 
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    /*
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    /*
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     * We do identity mapping of 4M-page at 4M.
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     * We do identity mapping of 4M-page at 4M.
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     */
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     */
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    tag.value = ASID_KERNEL;
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    tag.value = 0;
- 
 
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    tag.context = 0;
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    tag.vpn = pg.vpn;
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    tag.vpn = pg.vpn;
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    itlb_tag_access_write(tag.value);
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    dtlb_tag_access_write(tag.value);
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 - 
 
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    data.value = 0;
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    data.value = 0;
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    data.v = true;
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    data.v = true;
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    data.size = PAGESIZE_4M;
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    data.size = PAGESIZE_4M;
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    data.pfn = fr.pfn;
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    data.pfn = fr.pfn;
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    data.l = true;
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    data.l = true;
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    data.cp = 1;
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    data.cp = 1;
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    data.cv = 1;
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    data.cv = 0;
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    data.p = true;
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    data.p = true;
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    data.w = true;
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    data.w = true;
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    data.g = true;
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    data.g = true;
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- 
 
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    /*
- 
 
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     * Straightforwardly demap DMUU context 0,
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     * and replace it with the locked kernel mapping.
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     */
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    dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
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    itlb_data_in_write(data.value);
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    dtlb_tag_access_write(tag.value);
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    dtlb_data_in_write(data.value);
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    dtlb_data_in_write(data.value);
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    /*
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    /*
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     * Register window traps can occur before MMU is enabled again.
 - 
 
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     * This ensures that any such traps will be handled from
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     * Install kernel code mapping in context 1
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     * kernel identity mapped trap handler.
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     * and switch to it.
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     */
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     */
- 
 
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    tag.context = 1;
- 
 
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    data.g = false;
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    itlb_tag_access_write(tag.value);
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    itlb_data_in_write(data.value);
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    trap_switch_trap_table();
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    mmu_primary_context_write(1);
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- 
 
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    /*
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    tlb_invalidate_all();
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     * Demap old context 0.
- 
 
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     */
- 
 
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    itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
160 
 
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- 
 
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    /*
- 
 
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     * Install the locked kernel mapping in context 0
- 
 
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     * and switch to it.
- 
 
 168 
     */
161 
    dmmu_enable();
 169 
    tag.context = 0;
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    immu_enable();
 170 
    data.g = true;
- 
 
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    itlb_tag_access_write(tag.value);
- 
 
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    itlb_data_in_write(data.value);
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    mmu_primary_context_write(0);
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}
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}
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/** @}
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/** @}
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 */
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 */