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38 | #include <arch/console.h> |
38 | #include <arch/console.h> |
39 | #include <arch/drivers/tick.h> |
39 | #include <arch/drivers/tick.h> |
40 | #include <proc/thread.h> |
40 | #include <proc/thread.h> |
41 | #include <console/console.h> |
41 | #include <console/console.h> |
42 | #include <arch/boot/boot.h> |
42 | #include <arch/boot/boot.h> |
- | 43 | #include <arch/arch.h> |
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- | 44 | #include <arch/mm/tlb.h> |
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- | 45 | #include <mm/asid.h> |
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43 | 46 | ||
44 | bootinfo_t bootinfo; |
47 | bootinfo_t bootinfo; |
45 | 48 | ||
46 | void arch_pre_mm_init(void) |
49 | void arch_pre_mm_init(void) |
47 | { |
50 | { |
Line 86... | Line 89... | ||
86 | */ |
89 | */ |
87 | void arch_release_console(void) |
90 | void arch_release_console(void) |
88 | { |
91 | { |
89 | } |
92 | } |
90 | 93 | ||
- | 94 | /** Take over TLB and trap table. |
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- | 95 | * |
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- | 96 | * Initialize ITLB and DTLB and switch to kernel |
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- | 97 | * trap table. |
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- | 98 | * |
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- | 99 | * The goal of this function is to disable MMU |
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- | 100 | * so that both TLBs can be purged and new |
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- | 101 | * kernel 4M locked entry can be installed. |
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- | 102 | * After TLB is initialized, MMU is enabled |
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- | 103 | * again. |
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- | 104 | * |
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- | 105 | * Switching MMU off imposes the requirement for |
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- | 106 | * the kernel to run in identity mapped environment. |
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- | 107 | * |
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- | 108 | * @param base Base address that will be hardwired in both TLBs. |
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- | 109 | */ |
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- | 110 | void take_over_tlb_and_tt(uintptr_t base) |
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- | 111 | { |
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- | 112 | tlb_tag_access_reg_t tag; |
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- | 113 | tlb_data_t data; |
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- | 114 | frame_address_t fr; |
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- | 115 | page_address_t pg; |
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- | 116 | ||
- | 117 | fr.address = base; |
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- | 118 | pg.address = base; |
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- | 119 | ||
- | 120 | immu_disable(); |
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- | 121 | dmmu_disable(); |
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- | 122 | ||
- | 123 | /* |
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- | 124 | * Demap everything, especially OpenFirmware. |
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- | 125 | */ |
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- | 126 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
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- | 127 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
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- | 128 | ||
- | 129 | /* |
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- | 130 | * We do identity mapping of 4M-page at 4M. |
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- | 131 | */ |
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- | 132 | tag.value = ASID_KERNEL; |
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- | 133 | tag.vpn = pg.vpn; |
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- | 134 | ||
- | 135 | itlb_tag_access_write(tag.value); |
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- | 136 | dtlb_tag_access_write(tag.value); |
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- | 137 | ||
- | 138 | data.value = 0; |
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- | 139 | data.v = true; |
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- | 140 | data.size = PAGESIZE_4M; |
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- | 141 | data.pfn = fr.pfn; |
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- | 142 | data.l = true; |
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- | 143 | data.cp = 1; |
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- | 144 | data.cv = 1; |
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- | 145 | data.p = true; |
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- | 146 | data.w = true; |
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- | 147 | data.g = true; |
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- | 148 | ||
- | 149 | itlb_data_in_write(data.value); |
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- | 150 | dtlb_data_in_write(data.value); |
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- | 151 | ||
- | 152 | /* |
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- | 153 | * Register window traps can occur before MMU is enabled again. |
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- | 154 | * This ensures that any such traps will be handled from |
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- | 155 | * kernel identity mapped trap handler. |
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- | 156 | */ |
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- | 157 | trap_switch_trap_table(); |
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- | 158 | ||
- | 159 | tlb_invalidate_all(); |
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- | 160 | ||
- | 161 | dmmu_enable(); |
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- | 162 | immu_enable(); |
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- | 163 | } |
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- | 164 | ||
91 | /** @} |
165 | /** @} |
92 | */ |
166 | */ |