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 */
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 */
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/** @file
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/** @file
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 */
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 */
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#include <arch/mm/tsb.h>
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#include <arch/mm/tsb.h>
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#include <arch/mm/tlb.h>
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#include <arch/barrier.h>
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#include <mm/as.h>
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#include <mm/as.h>
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#include <arch/types.h>
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#include <arch/types.h>
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#include <typedefs.h>
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#include <typedefs.h>
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#include <macros.h>
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#include <debug.h>
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#define TSB_INDEX_MASK      ((1<<(21+1+TSB_SIZE-PAGE_WIDTH))-1)
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/** Invalidate portion of TSB.
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/** Invalidate portion of TSB.
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 *
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 *
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 * We assume that the address space is already locked.
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 * We assume that the address space is already locked.
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 * Note that respective portions of both TSBs
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 * are invalidated at a time.
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 *
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 *
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 * @param as Address space.
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 * @param as Address space.
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 * @param page First page to invalidate in TSB.
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 * @param page First page to invalidate in TSB.
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 * @param pages Number of pages to invalidate.
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 * @param pages Number of pages to invalidate. Value of (count_t) -1 means the whole TSB.
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 */
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 */
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void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
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void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
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{
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{
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    index_t i0, i;
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    count_t cnt;
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    ASSERT(as->arch.itsb && as->arch.dtsb);
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    i0 = (page >> PAGE_WIDTH) & TSB_INDEX_MASK;
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    cnt = min(pages, ITSB_ENTRY_COUNT);
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    for (i = 0; i < cnt; i++) {
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        as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT-1)].tag.invalid = 0;
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        as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT-1)].tag.invalid = 0;
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    }
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}
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/** Copy software PTE to ITSB.
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 *
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 * @param t Software PTE.
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 */
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void itsb_pte_copy(pte_t *t)
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{
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    as_t *as;
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    tsb_entry_t *tsb;
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    as = t->as;
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    tsb = &as->arch.itsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK];
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    /*
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     * We use write barriers to make sure that the TSB load
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     * won't use inconsistent data or that the fault will
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     * be repeated.
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     */
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    tsb->tag.invalid = 1;   /* invalidate the entry (tag target has this set to 0 */
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    write_barrier();
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    tsb->tag.context = as->asid;
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    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
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    tsb->data.value = 0;
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    tsb->data.size = PAGESIZE_8K;
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    tsb->data.pfn = t->frame >> PAGE_WIDTH;
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    tsb->data.cp = t->c;
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    tsb->data.cv = t->c;
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    tsb->data.p = t->k; /* p as privileged */
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    tsb->data.v = t->p;
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    write_barrier();
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    tsb->tag.invalid = 0;   /* mark the entry as valid */
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}
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/** Copy software PTE to DTSB.
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 *
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 * @param t Software PTE.
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 * @param ro If true, the mapping is copied read-only.
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 */
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void dtsb_pte_copy(pte_t *t, bool ro)
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{
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    as_t *as;
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    tsb_entry_t *tsb;
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    as = t->as;
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    tsb = &as->arch.dtsb[(t->page >> PAGE_WIDTH) & TSB_INDEX_MASK];
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    /*
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     * We use write barriers to make sure that the TSB load
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     * won't use inconsistent data or that the fault will
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     * be repeated.
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     */
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    tsb->tag.invalid = 1;   /* invalidate the entry (tag target has this set to 0) */
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    write_barrier();
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    tsb->tag.context = as->asid;
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    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
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    tsb->data.value = 0;
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    tsb->data.size = PAGESIZE_8K;
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    tsb->data.pfn = t->frame >> PAGE_WIDTH;
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    tsb->data.cp = t->c;
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    tsb->data.cv = t->c;
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    tsb->data.p = t->k; /* p as privileged */
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    tsb->data.w = ro ? false : t->w;
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    tsb->data.v = t->p;
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    write_barrier();
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    tsb->tag.invalid = 0;   /* mark the entry as valid */
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}
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}
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/** @}
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/** @}
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 */
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 */