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| Rev 1859 | Rev 1860 | ||
|---|---|---|---|
| Line 372... | Line 372... | ||
| 372 | * |
372 | * |
| 373 | * @param asid Address Space ID. |
373 | * @param asid Address Space ID. |
| 374 | */ |
374 | */ |
| 375 | void tlb_invalidate_asid(asid_t asid) |
375 | void tlb_invalidate_asid(asid_t asid) |
| 376 | { |
376 | { |
| - | 377 | tlb_context_reg_t sc_save, ctx; |
|
| - | 378 | ||
| 377 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
379 | ctx.v = sc_save.v = mmu_secondary_context_read(); |
| - | 380 | ctx.context = asid; |
|
| - | 381 | mmu_secondary_context_write(ctx.v); |
|
| - | 382 | ||
| 378 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
383 | itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_SECONDARY, 0); |
| 379 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
384 | dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_SECONDARY, 0); |
| - | 385 | ||
| - | 386 | mmu_secondary_context_write(sc_save.v); |
|
| 380 | } |
387 | } |
| 381 | 388 | ||
| 382 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
389 | /** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
| 383 | * |
390 | * |
| 384 | * @param asid Address Space ID. |
391 | * @param asid Address Space ID. |
| Line 386... | Line 393... | ||
| 386 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
393 | * @param cnt Number of ITLB and DTLB entries to invalidate. |
| 387 | */ |
394 | */ |
| 388 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
395 | void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
| 389 | { |
396 | { |
| 390 | int i; |
397 | int i; |
| - | 398 | tlb_context_reg_t sc_save, ctx; |
|
| - | 399 | ||
| - | 400 | ctx.v = sc_save.v = mmu_secondary_context_read(); |
|
| - | 401 | ctx.context = asid; |
|
| - | 402 | mmu_secondary_context_write(ctx.v); |
|
| 391 | 403 | ||
| 392 | for (i = 0; i < cnt; i++) { |
404 | for (i = 0; i < cnt; i++) { |
| 393 | /* TODO: write asid to some Context register and encode the register in second parameter below. */ |
- | |
| 394 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
405 | itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, page + i * PAGE_SIZE); |
| 395 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
406 | dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, page + i * PAGE_SIZE); |
| 396 | } |
407 | } |
| - | 408 | ||
| - | 409 | mmu_secondary_context_write(sc_save.v); |
|
| 397 | } |
410 | } |
| 398 | 411 | ||
| 399 | /** @} |
412 | /** @} |
| 400 | */ |
413 | */ |