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#include <arch/mm/as.h>
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#include <arch/mm/as.h>
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#include <arch/mm/tlb.h>
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#include <arch/mm/tlb.h>
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#include <genarch/mm/as_ht.h>
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#include <genarch/mm/as_ht.h>
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#include <genarch/mm/asid_fifo.h>
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#include <genarch/mm/asid_fifo.h>
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#include <debug.h>
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#ifdef CONFIG_TSB
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#include <arch/mm/tsb.h>
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#endif
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/** Architecture dependent address space init. */
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/** Architecture dependent address space init. */
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void as_arch_init(void)
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void as_arch_init(void)
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{
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{
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    as_operations = &as_ht_operations;
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    as_operations = &as_ht_operations;
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    asid_fifo_init();
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    asid_fifo_init();
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}
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}
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/** Perform sparc64-specific tasks when an address space becomes active on the processor.
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 *
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 * Install ASID and map TSBs.
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 *
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 * @param as Address space.
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 */
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void as_install_arch(as_t *as)
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void as_install_arch(as_t *as)
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{
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{
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    tlb_context_reg_t ctx;
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    tlb_context_reg_t ctx;
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    /*
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    /*
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     * Note that we don't lock the address space.
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     * That's correct - we can afford it here
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     * because we only read members that are
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     * currently read-only.
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     */
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    /*
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     * Write ASID to secondary context register.
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     * Write ASID to secondary context register.
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     * The primary context register has to be set
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     * The primary context register has to be set
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     * from TL>0 so it will be filled from the
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     * from TL>0 so it will be filled from the
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     * secondary context register from the TL=1
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     * secondary context register from the TL=1
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     * code just before switch to userspace.
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     * code just before switch to userspace.
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     */
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     */
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    ctx.v = 0;
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    ctx.v = 0;
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    ctx.context = as->asid;
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    ctx.context = as->asid;
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    mmu_secondary_context_write(ctx.v);
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    mmu_secondary_context_write(ctx.v);
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#ifdef CONFIG_TSB  
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    if (as != AS_KERNEL) {
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        uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
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        ASSERT(as->arch.itsb && as->arch.dtsb);
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        uintptr_t tsb = as->arch.itsb;
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        if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
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            /*
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             * TSBs were allocated from memory not covered
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             * by the locked 4M kernel DTLB entry. We need
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             * to map both TSBs explicitly.
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             */
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            dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
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            dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
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        }
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        /*
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         * Setup TSB Base registers.
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         */
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        tsb_base_reg_t tsb_base;
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        tsb_base.value = 0;
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        tsb_base.size = TSB_SIZE;
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        tsb_base.split = 0;
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        tsb_base.base = as->arch.itsb >> PAGE_WIDTH;
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        itsb_base_write(tsb_base.value);
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        tsb_base.base = as->arch.dtsb >> PAGE_WIDTH;
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        dtsb_base_write(tsb_base.value);
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    }
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#endif
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}
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/** Perform sparc64-specific tasks when an address space is removed from the processor.
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 *
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 * Demap TSBs.
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 *
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 * @param as Address space.
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 */
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void as_deinstall_arch(as_t *as)
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{
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    /*
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     * Note that we don't lock the address space.
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     * That's correct - we can afford it here
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     * because we only read members that are
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     * currently read-only.
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     */
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#ifdef CONFIG_TSB
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    if (as != AS_KERNEL) {
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        uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
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        ASSERT(as->arch.itsb && as->arch.dtsb);
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        uintptr_t tsb = as->arch.itsb;
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        if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
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            /*
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             * TSBs were allocated from memory not covered
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             * by the locked 4M kernel DTLB entry. We need
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             * to demap the entry installed by as_install_arch().
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             */
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            dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
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        }
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    }
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#endif
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}
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}
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/** @}
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/** @}
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 */
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 */