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Line 127... | Line 127... | ||
127 | 0: |
127 | 0: |
128 | .if (\tl > 0) |
128 | .if (\tl > 0) |
129 | wrpr %g0, 1, %tl |
129 | wrpr %g0, 1, %tl |
130 | .endif |
130 | .endif |
131 | 131 | ||
- | 132 | /* |
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- | 133 | * Switch from the MM globals. |
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- | 134 | */ |
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132 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
135 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
- | 136 | ||
- | 137 | /* |
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- | 138 | * Read the Tag Access register for the higher-level handler. |
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- | 139 | * This is necessary to survive nested DTLB misses. |
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- | 140 | */ |
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- | 141 | mov VA_DMMU_TAG_ACCESS, %g2 |
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- | 142 | ldxa [%g2] ASI_DMMU, %g2 |
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- | 143 | ||
- | 144 | /* |
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- | 145 | * g2 will be passed as an argument to fast_data_access_mmu_miss(). |
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- | 146 | */ |
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133 | PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |
147 | PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |
134 | .endm |
148 | .endm |
135 | 149 | ||
136 | .macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl |
150 | .macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl |
137 | /* |
151 | /* |
Line 140... | Line 154... | ||
140 | 154 | ||
141 | .if (\tl > 0) |
155 | .if (\tl > 0) |
142 | wrpr %g0, 1, %tl |
156 | wrpr %g0, 1, %tl |
143 | .endif |
157 | .endif |
144 | 158 | ||
- | 159 | /* |
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- | 160 | * Switch from the MM globals. |
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- | 161 | */ |
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145 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
162 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
- | 163 | ||
- | 164 | /* |
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- | 165 | * Read the Tag Access register for the higher-level handler. |
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- | 166 | * This is necessary to survive nested DTLB misses. |
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- | 167 | */ |
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- | 168 | mov VA_DMMU_TAG_ACCESS, %g2 |
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- | 169 | ldxa [%g2] ASI_DMMU, %g2 |
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- | 170 | ||
- | 171 | /* |
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- | 172 | * g2 will be passed as an argument to fast_data_access_mmu_miss(). |
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- | 173 | */ |
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146 | PREEMPTIBLE_HANDLER fast_data_access_protection |
174 | PREEMPTIBLE_HANDLER fast_data_access_protection |
147 | .endm |
175 | .endm |
148 | 176 | ||
149 | #endif /* __ASM__ */ |
177 | #endif /* __ASM__ */ |
150 | 178 |