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| 40 | #include <arch/stack.h> |
40 | #include <arch/stack.h> |
| 41 | #include <arch/regdef.h> |
41 | #include <arch/regdef.h> |
| 42 | #include <arch/mm/tlb.h> |
42 | #include <arch/mm/tlb.h> |
| 43 | #include <arch/mm/mmu.h> |
43 | #include <arch/mm/mmu.h> |
| 44 | #include <arch/mm/tte.h> |
44 | #include <arch/mm/tte.h> |
| - | 45 | #include <arch/trap/regwin.h> |
|
| 45 | 46 | ||
| 46 | #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 |
47 | #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 |
| 47 | #define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 |
48 | #define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 |
| 48 | #define TT_FAST_DATA_ACCESS_PROTECTION 0x6c |
49 | #define TT_FAST_DATA_ACCESS_PROTECTION 0x6c |
| 49 | 50 | ||
| 50 | #define FAST_MMU_HANDLER_SIZE 128 |
51 | #define FAST_MMU_HANDLER_SIZE 128 |
| 51 | 52 | ||
| 52 | #ifdef __ASM__ |
53 | #ifdef __ASM__ |
| - | 54 | ||
| 53 | .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER |
55 | .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER |
| 54 | /* |
56 | ! |
| 55 | * First, try to refill TLB from TSB. |
57 | ! First, try to refill TLB from TSB. |
| 56 | */ |
58 | ! |
| 57 | ! TODO |
59 | ! TODO |
| 58 | 60 | ||
| 59 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
61 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
| 60 | PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss |
62 | PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss |
| 61 | .endm |
63 | .endm |
| Line 72... | Line 74... | ||
| 72 | * identity mapping for that page in DTLB. VPN 0 is excluded from |
74 | * identity mapping for that page in DTLB. VPN 0 is excluded from |
| 73 | * this treatment. |
75 | * this treatment. |
| 74 | * |
76 | * |
| 75 | * Note that branch-delay slots are used in order to save space. |
77 | * Note that branch-delay slots are used in order to save space. |
| 76 | */ |
78 | */ |
| 77 | 0: |
79 | |
| 78 | mov VA_DMMU_TAG_ACCESS, %g1 |
80 | mov VA_DMMU_TAG_ACCESS, %g1 |
| 79 | ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN |
81 | ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN |
| 80 | set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 |
82 | set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 |
| 81 | andcc %g1, %g2, %g3 ! get Context |
83 | andcc %g1, %g2, %g3 ! get Context |
| 82 | bnz 0f ! Context is non-zero |
84 | bnz 0f ! Context is non-zero |
| 83 | andncc %g1, %g2, %g3 ! get page address into %g3 |
85 | andncc %g1, %g2, %g3 ! get page address into %g3 |
| 84 | bz 0f ! page address is zero |
86 | bz 0f ! page address is zero |
| 85 | 87 | ||
| 86 | or %g3, (TTE_CP|TTE_P|TTE_W), %g2 ! 8K pages are the default (encoded as 0) |
88 | or %g3, (TTE_CP|TTE_P|TTE_W), %g2 ! 8K pages are the default (encoded as 0) |
| 87 | set 1, %g3 |
89 | mov 1, %g3 |
| 88 | sllx %g3, TTE_V_SHIFT, %g3 |
90 | sllx %g3, TTE_V_SHIFT, %g3 |
| 89 | or %g2, %g3, %g2 |
91 | or %g2, %g3, %g2 |
| 90 | stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page |
92 | stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page |
| 91 | retry |
93 | retry |
| 92 | 94 | ||
| 93 | /* |
95 | /* |
| 94 | * Third, catch and handle special cases when the trap is caused by |
96 | * Third, catch and handle special cases when the trap is caused by |
| 95 | * some register window trap handler. |
97 | * the userspace register window spill or fill handler. In case |
| - | 98 | * one of these two traps caused this trap, we just lower the trap |
|
| - | 99 | * level and service the DTLB miss. In the end, we restart |
|
| - | 100 | * the offending SAVE or RESTORE. |
|
| 96 | */ |
101 | */ |
| 97 | 0: |
102 | 0: |
| 98 | ! TODO |
103 | HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL |
| 99 | 104 | ||
| 100 | 0: |
- | |
| 101 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
105 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
| 102 | PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |
106 | PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |
| 103 | .endm |
107 | .endm |
| 104 | 108 | ||
| 105 | .macro FAST_DATA_ACCESS_PROTECTION_HANDLER |
109 | .macro FAST_DATA_ACCESS_PROTECTION_HANDLER |
| - | 110 | /* |
|
| - | 111 | * First, try to refill TLB from TSB. |
|
| - | 112 | */ |
|
| - | 113 | ! TODO |
|
| - | 114 | ||
| - | 115 | /* |
|
| - | 116 | * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. |
|
| - | 117 | */ |
|
| - | 118 | HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL |
|
| - | 119 | ||
| 106 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
120 | wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
| 107 | PREEMPTIBLE_HANDLER fast_data_access_protection |
121 | PREEMPTIBLE_HANDLER fast_data_access_protection |
| 108 | .endm |
122 | .endm |
| - | 123 | ||
| - | 124 | /* |
|
| - | 125 | * Macro used to lower TL when a MMU trap is caused by |
|
| - | 126 | * the userspace register window spill or fill handler. |
|
| - | 127 | */ |
|
| - | 128 | .macro HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL |
|
| - | 129 | rdpr %tl, %g1 |
|
| - | 130 | dec %g1 |
|
| - | 131 | brz %g1, 0f ! if TL was 1, skip |
|
| - | 132 | nop |
|
| - | 133 | wrpr %g1, 0, %tl ! TL-- |
|
| - | 134 | rdpr %tt, %g2 |
|
| - | 135 | cmp %g2, TT_SPILL_1_NORMAL |
|
| - | 136 | be 0f ! trap from spill_1_normal |
|
| - | 137 | cmp %g2, TT_FILL_1_NORMAL |
|
| - | 138 | be 0f ! trap from fill_1_normal |
|
| - | 139 | inc %g1 |
|
| - | 140 | wrpr %g1, 0, %tl ! another trap, TL++ |
|
| - | 141 | 0: |
|
| - | 142 | .endm |
|
| - | 143 | ||
| 109 | #endif /* __ASM__ */ |
144 | #endif /* __ASM__ */ |
| 110 | 145 | ||
| 111 | #endif |
146 | #endif |
| 112 | 147 | ||
| 113 | /** @} |
148 | /** @} |