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56 | * Implementation of generic 4-level page table interface. |
56 | * Implementation of generic 4-level page table interface. |
57 | * |
57 | * |
58 | * Page table layout: |
58 | * Page table layout: |
59 | * - 32-bit virtual addresses |
59 | * - 32-bit virtual addresses |
60 | * - Offset is 14 bits => pages are 16K long |
60 | * - Offset is 14 bits => pages are 16K long |
61 | * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long |
61 | * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore |
- | 62 | * 4 bytes long |
|
62 | * - PTE's replace EntryLo v (valid) bit with p (present) bit |
63 | * - PTE's replace EntryLo v (valid) bit with p (present) bit |
63 | * - PTE's use only one bit to distinguish between cacheable and uncacheable mappings |
64 | * - PTE's use only one bit to distinguish between cacheable and uncacheable |
- | 65 | * mappings |
|
64 | * - PTE's define soft_valid field to ensure there is at least one 1 bit even if the p bit is cleared |
66 | * - PTE's define soft_valid field to ensure there is at least one 1 bit even if |
- | 67 | * the p bit is cleared |
|
65 | * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed) |
68 | * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) |
- | 69 | * and bit A (accessed) |
|
66 | * - PTL0 has 64 entries (6 bits) |
70 | * - PTL0 has 64 entries (6 bits) |
67 | * - PTL1 is not used |
71 | * - PTL1 is not used |
68 | * - PTL2 is not used |
72 | * - PTL2 is not used |
69 | * - PTL3 has 4096 entries (12 bits) |
73 | * - PTL3 has 4096 entries (12 bits) |
70 | */ |
74 | */ |
71 | 75 | ||
- | 76 | /* Macros describing number of entries in each level. */ |
|
72 | #define PTL0_ENTRIES_ARCH 64 |
77 | #define PTL0_ENTRIES_ARCH 64 |
73 | #define PTL1_ENTRIES_ARCH 0 |
78 | #define PTL1_ENTRIES_ARCH 0 |
74 | #define PTL2_ENTRIES_ARCH 0 |
79 | #define PTL2_ENTRIES_ARCH 0 |
75 | #define PTL3_ENTRIES_ARCH 4096 |
80 | #define PTL3_ENTRIES_ARCH 4096 |
76 | 81 | ||
- | 82 | /* Macros describing size of page tables in each level. */ |
|
77 | #define PTL0_SIZE_ARCH ONE_FRAME |
83 | #define PTL0_SIZE_ARCH ONE_FRAME |
78 | #define PTL1_SIZE_ARCH 0 |
84 | #define PTL1_SIZE_ARCH 0 |
79 | #define PTL2_SIZE_ARCH 0 |
85 | #define PTL2_SIZE_ARCH 0 |
80 | #define PTL3_SIZE_ARCH ONE_FRAME |
86 | #define PTL3_SIZE_ARCH ONE_FRAME |
81 | 87 | ||
- | 88 | /* Macros calculating entry indices for each level. */ |
|
82 | #define PTL0_INDEX_ARCH(vaddr) ((vaddr)>>26) |
89 | #define PTL0_INDEX_ARCH(vaddr) ((vaddr) >> 26) |
83 | #define PTL1_INDEX_ARCH(vaddr) 0 |
90 | #define PTL1_INDEX_ARCH(vaddr) 0 |
84 | #define PTL2_INDEX_ARCH(vaddr) 0 |
91 | #define PTL2_INDEX_ARCH(vaddr) 0 |
85 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>14) & 0xfff) |
92 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 14) & 0xfff) |
86 | 93 | ||
- | 94 | /* Set accessor for PTL0 address. */ |
|
87 | #define SET_PTL0_ADDRESS_ARCH(ptl0) |
95 | #define SET_PTL0_ADDRESS_ARCH(ptl0) |
88 | 96 | ||
- | 97 | /* Get PTE address accessors for each level. */ |
|
89 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].pfn<<12) |
98 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ |
- | 99 | (((pte_t *) (ptl0))[(i)].pfn << 12) |
|
90 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
100 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ |
- | 101 | (ptl1) |
|
91 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
102 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ |
- | 103 | (ptl2) |
|
92 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *)(ptl3))[(i)].pfn<<12) |
104 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ |
- | 105 | (((pte_t *) (ptl3))[(i)].pfn << 12) |
|
93 | 106 | ||
- | 107 | /* Set PTE address accessors for each level. */ |
|
94 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].pfn = (a)>>12) |
108 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
- | 109 | (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12) |
|
95 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
110 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
96 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
111 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
97 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].pfn = (a)>>12) |
- | |
98 | - | ||
99 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i)) |
- | |
100 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
112 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
101 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
113 | (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12) |
102 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i)) |
- | |
103 | 114 | ||
- | 115 | /* Get PTE flags accessors for each level. */ |
|
- | 116 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
|
- | 117 | get_pt_flags((pte_t *) (ptl0), (index_t) (i)) |
|
- | 118 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
|
- | 119 | PAGE_PRESENT |
|
- | 120 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
|
- | 121 | PAGE_PRESENT |
|
- | 122 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
|
- | 123 | get_pt_flags((pte_t *) (ptl3), (index_t) (i)) |
|
- | 124 | ||
- | 125 | /* Set PTE flags accessors for each level. */ |
|
- | 126 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
|
104 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x)) |
127 | set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x)) |
105 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
128 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
106 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
129 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
- | 130 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
|
107 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x)) |
131 | set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x)) |
108 | 132 | ||
- | 133 | /* Last-level info macros. */ |
|
109 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
134 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
110 | #define PTE_PRESENT_ARCH(pte) ((pte)->p != 0) |
135 | #define PTE_PRESENT_ARCH(pte) ((pte)->p != 0) |
111 | #define PTE_GET_FRAME_ARCH(pte) ((pte)->pfn<<12) |
136 | #define PTE_GET_FRAME_ARCH(pte) ((pte)->pfn << 12) |
112 | #define PTE_WRITABLE_ARCH(pte) ((pte)->w != 0) |
137 | #define PTE_WRITABLE_ARCH(pte) ((pte)->w != 0) |
113 | #define PTE_EXECUTABLE_ARCH(pte) 1 |
138 | #define PTE_EXECUTABLE_ARCH(pte) 1 |
114 | 139 | ||
115 | #ifndef __ASM__ |
140 | #ifndef __ASM__ |
116 | 141 | ||
Line 119... | Line 144... | ||
119 | 144 | ||
120 | static inline int get_pt_flags(pte_t *pt, index_t i) |
145 | static inline int get_pt_flags(pte_t *pt, index_t i) |
121 | { |
146 | { |
122 | pte_t *p = &pt[i]; |
147 | pte_t *p = &pt[i]; |
123 | 148 | ||
124 | return ( |
- | |
125 | (p->cacheable<<PAGE_CACHEABLE_SHIFT) | |
149 | return ((p->cacheable << PAGE_CACHEABLE_SHIFT) | |
126 | ((!p->p)<<PAGE_PRESENT_SHIFT) | |
150 | ((!p->p) << PAGE_PRESENT_SHIFT) | |
127 | (1<<PAGE_USER_SHIFT) | |
151 | (1 << PAGE_USER_SHIFT) | |
128 | (1<<PAGE_READ_SHIFT) | |
152 | (1 << PAGE_READ_SHIFT) | |
129 | ((p->w)<<PAGE_WRITE_SHIFT) | |
153 | ((p->w) << PAGE_WRITE_SHIFT) | |
130 | (1<<PAGE_EXEC_SHIFT) | |
154 | (1 << PAGE_EXEC_SHIFT) | |
131 | (p->g<<PAGE_GLOBAL_SHIFT) |
155 | (p->g << PAGE_GLOBAL_SHIFT)); |
132 | ); |
- | |
133 | - | ||
134 | } |
156 | } |
135 | 157 | ||
136 | static inline void set_pt_flags(pte_t *pt, index_t i, int flags) |
158 | static inline void set_pt_flags(pte_t *pt, index_t i, int flags) |
137 | { |
159 | { |
138 | pte_t *p = &pt[i]; |
160 | pte_t *p = &pt[i]; |