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 * Implementation of generic 4-level page table interface.
 56 
 * Implementation of generic 4-level page table interface.
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 *
 57 
 *
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 * Page table layout:
 58 
 * Page table layout:
59 
 * - 32-bit virtual addresses
 59 
 * - 32-bit virtual addresses
60 
 * - Offset is 14 bits => pages are 16K long
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 * - Offset is 14 bits => pages are 16K long
61 
 * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long
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 * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore
- 
 
 62 
 *   4 bytes long
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 * - PTE's replace EntryLo v (valid) bit with p (present) bit
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 * - PTE's replace EntryLo v (valid) bit with p (present) bit
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 * - PTE's use only one bit to distinguish between cacheable and uncacheable mappings
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 * - PTE's use only one bit to distinguish between cacheable and uncacheable
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 65 
 *   mappings
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 * - PTE's define soft_valid field to ensure there is at least one 1 bit even if the p bit is cleared
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 * - PTE's define soft_valid field to ensure there is at least one 1 bit even if
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 *   the p bit is cleared
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 * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed)
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 * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable)
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 69 
 *   and bit A (accessed)
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 * - PTL0 has 64 entries (6 bits)
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 * - PTL0 has 64 entries (6 bits)
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 * - PTL1 is not used
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 * - PTL1 is not used
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 * - PTL2 is not used
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 * - PTL2 is not used
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 * - PTL3 has 4096 entries (12 bits)
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 * - PTL3 has 4096 entries (12 bits)
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 */
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 */
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 75 
 
- 
 
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/* Macros describing number of entries in each level. */
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#define PTL0_ENTRIES_ARCH   64
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#define PTL0_ENTRIES_ARCH   64
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#define PTL1_ENTRIES_ARCH   0
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#define PTL1_ENTRIES_ARCH   0
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#define PTL2_ENTRIES_ARCH   0
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#define PTL2_ENTRIES_ARCH   0
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#define PTL3_ENTRIES_ARCH   4096
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#define PTL3_ENTRIES_ARCH   4096
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 81 
 
- 
 
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/* Macros describing size of page tables in each level. */
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#define PTL0_SIZE_ARCH       ONE_FRAME
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#define PTL0_SIZE_ARCH      ONE_FRAME
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#define PTL1_SIZE_ARCH       0
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#define PTL1_SIZE_ARCH      0
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#define PTL2_SIZE_ARCH       0
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#define PTL2_SIZE_ARCH      0
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#define PTL3_SIZE_ARCH       ONE_FRAME
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#define PTL3_SIZE_ARCH      ONE_FRAME
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 87 
 
- 
 
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/* Macros calculating entry indices for each level. */
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#define PTL0_INDEX_ARCH(vaddr)  ((vaddr)>>26)
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#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26)
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#define PTL1_INDEX_ARCH(vaddr)  0
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#define PTL1_INDEX_ARCH(vaddr)  0
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#define PTL2_INDEX_ARCH(vaddr)  0
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#define PTL2_INDEX_ARCH(vaddr)  0
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#define PTL3_INDEX_ARCH(vaddr)  (((vaddr)>>14) & 0xfff)
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#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
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 93 
 
- 
 
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/* Set accessor for PTL0 address. */
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#define SET_PTL0_ADDRESS_ARCH(ptl0)
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#define SET_PTL0_ADDRESS_ARCH(ptl0)
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 96 
 
- 
 
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/* Get PTE address accessors for each level. */
89 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      (((pte_t *)(ptl0))[(i)].pfn<<12)
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#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
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    (((pte_t *) (ptl0))[(i)].pfn << 12)
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#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
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#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
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    (ptl1)
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#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
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#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
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    (ptl2)
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#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     (((pte_t *)(ptl3))[(i)].pfn<<12)
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#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
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    (((pte_t *) (ptl3))[(i)].pfn << 12)
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 106 
 
- 
 
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/* Set PTE address accessors for each level. */
94 
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)   (((pte_t *)(ptl0))[(i)].pfn = (a)>>12)
 108 
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
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    (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
95 
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
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#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)  (((pte_t *)(ptl3))[(i)].pfn = (a)>>12)
 - 
 
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 - 
 
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#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_flags((pte_t *)(ptl0), (index_t)(i))
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#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
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#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
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#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
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    (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
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#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_flags((pte_t *)(ptl3), (index_t)(i))
 - 
 
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 114 
 
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/* Get PTE flags accessors for each level. */
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#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
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    get_pt_flags((pte_t *) (ptl0), (index_t) (i))
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#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
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    PAGE_PRESENT
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#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
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    PAGE_PRESENT
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#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
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    get_pt_flags((pte_t *) (ptl3), (index_t) (i))
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- 
 
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/* Set PTE flags accessors for each level. */
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 126 
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
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#define SET_PTL1_FLAGS_ARCH(ptl0, i, x)     set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
 127 
    set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
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#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
 128 
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
106 
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
 129 
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
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#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
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#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)    set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
 131 
    set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
108 
 
 132 
 
- 
 
 133 
/* Last-level info macros. */
109 
#define PTE_VALID_ARCH(pte)         (*((uint32_t *) (pte)) != 0)
 134 
#define PTE_VALID_ARCH(pte)         (*((uint32_t *) (pte)) != 0)
110 
#define PTE_PRESENT_ARCH(pte)           ((pte)->p != 0)
 135 
#define PTE_PRESENT_ARCH(pte)           ((pte)->p != 0)
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#define PTE_GET_FRAME_ARCH(pte)         ((pte)->pfn<<12)
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#define PTE_GET_FRAME_ARCH(pte)         ((pte)->pfn << 12)
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#define PTE_WRITABLE_ARCH(pte)          ((pte)->w != 0)
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#define PTE_WRITABLE_ARCH(pte)          ((pte)->w != 0)
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#define PTE_EXECUTABLE_ARCH(pte)        1
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#define PTE_EXECUTABLE_ARCH(pte)        1
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 139 
 
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#ifndef __ASM__
 140 
#ifndef __ASM__
116 
 
 141 
 
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 144 
 
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static inline int get_pt_flags(pte_t *pt, index_t i)
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static inline int get_pt_flags(pte_t *pt, index_t i)
121 
{
 146 
{
122 
    pte_t *p = &pt[i];
 147 
    pte_t *p = &pt[i];
123 
   
 148 
   
124 
    return (
 - 
 
125 
        (p->cacheable<<PAGE_CACHEABLE_SHIFT) |
 149 
    return ((p->cacheable << PAGE_CACHEABLE_SHIFT) |
126 
        ((!p->p)<<PAGE_PRESENT_SHIFT) |
 150 
        ((!p->p) << PAGE_PRESENT_SHIFT) |
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        (1<<PAGE_USER_SHIFT) |
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        (1 << PAGE_USER_SHIFT) |
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        (1<<PAGE_READ_SHIFT) |
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        (1 << PAGE_READ_SHIFT) |
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        ((p->w)<<PAGE_WRITE_SHIFT) |
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        ((p->w) << PAGE_WRITE_SHIFT) |
130 
        (1<<PAGE_EXEC_SHIFT) |
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        (1 << PAGE_EXEC_SHIFT) |
131 
        (p->g<<PAGE_GLOBAL_SHIFT)
 155 
        (p->g << PAGE_GLOBAL_SHIFT));
132 
    );
 - 
 
133 
       
 - 
 
134 
}
 156 
}
135 
 
 157 
 
136 
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
 158 
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
137 
{
 159 
{
138 
    pte_t *p = &pt[i];
 160 
    pte_t *p = &pt[i];