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| Rev 2071 | Rev 2082 | ||
|---|---|---|---|
| Line 192... | Line 192... | ||
| 192 | */ |
192 | */ |
| 193 | static inline uint64_t thash(uint64_t va) |
193 | static inline uint64_t thash(uint64_t va) |
| 194 | { |
194 | { |
| 195 | uint64_t ret; |
195 | uint64_t ret; |
| 196 | 196 | ||
| 197 | __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); |
197 | asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); |
| 198 | 198 | ||
| 199 | return ret; |
199 | return ret; |
| 200 | } |
200 | } |
| 201 | 201 | ||
| 202 | /** Return Translation Hashed Entry Tag. |
202 | /** Return Translation Hashed Entry Tag. |
| Line 210... | Line 210... | ||
| 210 | */ |
210 | */ |
| 211 | static inline uint64_t ttag(uint64_t va) |
211 | static inline uint64_t ttag(uint64_t va) |
| 212 | { |
212 | { |
| 213 | uint64_t ret; |
213 | uint64_t ret; |
| 214 | 214 | ||
| 215 | __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); |
215 | asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); |
| 216 | 216 | ||
| 217 | return ret; |
217 | return ret; |
| 218 | } |
218 | } |
| 219 | 219 | ||
| 220 | /** Read Region Register. |
220 | /** Read Region Register. |
| Line 225... | Line 225... | ||
| 225 | */ |
225 | */ |
| 226 | static inline uint64_t rr_read(index_t i) |
226 | static inline uint64_t rr_read(index_t i) |
| 227 | { |
227 | { |
| 228 | uint64_t ret; |
228 | uint64_t ret; |
| 229 | ASSERT(i < REGION_REGISTERS); |
229 | ASSERT(i < REGION_REGISTERS); |
| 230 | __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT)); |
230 | asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT)); |
| 231 | return ret; |
231 | return ret; |
| 232 | } |
232 | } |
| 233 | 233 | ||
| 234 | /** Write Region Register. |
234 | /** Write Region Register. |
| 235 | * |
235 | * |
| Line 237... | Line 237... | ||
| 237 | * @param v Value to be written to rr[i]. |
237 | * @param v Value to be written to rr[i]. |
| 238 | */ |
238 | */ |
| 239 | static inline void rr_write(index_t i, uint64_t v) |
239 | static inline void rr_write(index_t i, uint64_t v) |
| 240 | { |
240 | { |
| 241 | ASSERT(i < REGION_REGISTERS); |
241 | ASSERT(i < REGION_REGISTERS); |
| 242 | __asm__ volatile ( |
242 | asm volatile ( |
| 243 | "mov rr[%0] = %1\n" |
243 | "mov rr[%0] = %1\n" |
| 244 | : |
244 | : |
| 245 | : "r" (i << VRN_SHIFT), "r" (v) |
245 | : "r" (i << VRN_SHIFT), "r" (v) |
| 246 | ); |
246 | ); |
| 247 | } |
247 | } |
| Line 252... | Line 252... | ||
| 252 | */ |
252 | */ |
| 253 | static inline uint64_t pta_read(void) |
253 | static inline uint64_t pta_read(void) |
| 254 | { |
254 | { |
| 255 | uint64_t ret; |
255 | uint64_t ret; |
| 256 | 256 | ||
| 257 | __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret)); |
257 | asm volatile ("mov %0 = cr.pta\n" : "=r" (ret)); |
| 258 | 258 | ||
| 259 | return ret; |
259 | return ret; |
| 260 | } |
260 | } |
| 261 | 261 | ||
| 262 | /** Write Page Table Register. |
262 | /** Write Page Table Register. |
| 263 | * |
263 | * |
| 264 | * @param v New value to be stored in PTA. |
264 | * @param v New value to be stored in PTA. |
| 265 | */ |
265 | */ |
| 266 | static inline void pta_write(uint64_t v) |
266 | static inline void pta_write(uint64_t v) |
| 267 | { |
267 | { |
| 268 | __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v)); |
268 | asm volatile ("mov cr.pta = %0\n" : : "r" (v)); |
| 269 | } |
269 | } |
| 270 | 270 | ||
| 271 | extern void page_arch_init(void); |
271 | extern void page_arch_init(void); |
| 272 | 272 | ||
| 273 | extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid); |
273 | extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid); |