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Line 97... | Line 97... | ||
97 | jmp %o7 + 8 ! exit point |
97 | jmp %o7 + 8 ! exit point |
98 | mov %o1, %o0 |
98 | mov %o1, %o0 |
99 | 99 | ||
100 | jump_to_kernel: |
100 | jump_to_kernel: |
101 | /* |
101 | /* |
102 | * Make sure that the code we have moved has drained to main memory. |
102 | * We have copied code and now we need to guarantee cache coherence. |
103 | * We have a reason to assume that the I-cache does not include the |
103 | * 1. Make sure that the code we have moved has drained to main memory. |
104 | * code to which we are going to pass control. Hence no I-cache |
104 | * 2. Invalidate I-cache. |
105 | * invalidation. |
105 | * 3. Flush instruction pipeline. |
106 | */ |
106 | */ |
- | 107 | call icache_flush |
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107 | membar #StoreStore |
108 | membar #StoreStore |
- | 109 | flush %i7 |
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108 | 110 | ||
109 | mov %o0, %l1 |
111 | mov %o0, %l1 |
110 | mov %o1, %o0 |
112 | mov %o1, %o0 |
111 | mov %o2, %o1 |
113 | mov %o2, %o1 |
112 | mov %o3, %o2 |
114 | mov %o3, %o2 |
113 | jmp %l1 ! jump to kernel |
115 | jmp %l1 ! jump to kernel |
114 | nop |
116 | nop |
115 | 117 | ||
- | 118 | #define ICACHE_SIZE 8192 |
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- | 119 | #define ICACHE_LINE_SIZE 32 |
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- | 120 | #define ICACHE_SET_BIT (1 << 13) |
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- | 121 | #define ASI_ICACHE_TAG 0x67 |
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- | 122 | ||
- | 123 | # Flush I-cache |
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- | 124 | icache_flush: |
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- | 125 | set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1 |
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- | 126 | stxa %g0, [%g1] ASI_ICACHE_TAG |
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- | 127 | 0: membar #Sync |
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- | 128 | subcc %g1, ICACHE_LINE_SIZE, %g1 |
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- | 129 | bnz,pt %xcc, 0b |
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- | 130 | stxa %g0, [%g1] ASI_ICACHE_TAG |
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- | 131 | membar #Sync |
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- | 132 | retl |
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- | 133 | ! SF Erratum #51 |
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- | 134 | nop |
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- | 135 | ||
116 | .global ofw |
136 | .global ofw |
117 | ofw: |
137 | ofw: |
118 | save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
138 | save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
119 | set ofw_cif, %l0 |
139 | set ofw_cif, %l0 |
120 | ldx [%l0], %l0 |
140 | ldx [%l0], %l0 |