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/*

/*

 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt

 * Copyright (c) 2007 Pavel Jancik

 * All rights reserved.

 * Copyright (c) 2007 Michal Kebrt

 *

 * All rights reserved.

 * Redistribution and use in source and binary forms, with or without

 *

 * modification, are permitted provided that the following conditions

 * Redistribution and use in source and binary forms, with or without

 * are met:

 * modification, are permitted provided that the following conditions

 *

 * are met:

 * - Redistributions of source code must retain the above copyright

 *

 *   notice, this list of conditions and the following disclaimer.

 * - Redistributions of source code must retain the above copyright

 * - Redistributions in binary form must reproduce the above copyright

 *   notice, this list of conditions and the following disclaimer.

 *   notice, this list of conditions and the following disclaimer in the

 * - Redistributions in binary form must reproduce the above copyright

 *   documentation and/or other materials provided with the distribution.

 *   notice, this list of conditions and the following disclaimer in the

 * - The name of the author may not be used to endorse or promote products

 *   documentation and/or other materials provided with the distribution.

 *   derived from this software without specific prior written permission.

 * - The name of the author may not be used to endorse or promote products

 *

 *   derived from this software without specific prior written permission.

 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR

 *

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR

 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.

 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,

 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.

 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT

 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,

 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT

 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF

 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF

 */

 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

/** @addtogroup arm32boot

 * @{

/** @addtogroup arm32boot

 */

 * @{

/** @file

 */

 *  @brief Memory management used while booting the kernel.

/** @file

 *

 *  @brief Memory management used while booting the kernel.

 *  So called "section" paging is used while booting the kernel. The term "section"

 *

 *  comes from the ARM architecture specification and stands for the following:

 *  So called "section" paging is used while booting the kernel. The term

 *  one-level paging, 1MB sized pages, 4096 entries in the page table.

 *  "section" comes from the ARM architecture specification and stands for the

 */

 *  following: one-level paging, 1MB sized pages, 4096 entries in the page

 *  table.

 */

#ifndef BOOT_arm32__MM_H

#define BOOT_arm32__MM_H

#ifndef BOOT_arm32__MM_H

#define BOOT_arm32__MM_H

#ifndef __ASM__

#include "types.h"

#endif

#ifndef __ASM__

#include "types.h"

#endif

/** Frame width. */

#define FRAME_WIDTH                 20

/** Frame width. */

/** Frame size. */

#define FRAME_WIDTH         20

#define FRAME_SIZE                  (1 << FRAME_WIDTH)

/** Frame size. */

/** Page size in 2-level paging which is switched on later after the kernel initialization. */

#define FRAME_SIZE          (1 << FRAME_WIDTH)

#define KERNEL_PAGE_SIZE            (1 << 12)

/** Page size in 2-level paging which is switched on later after the kernel

 * initialization.

#ifndef __ASM__

 */

/** Converts kernel address to physical address. */

#define KERNEL_PAGE_SIZE        (1 << 12)

#   define KA2PA(x)                 (((uintptr_t) (x)) - 0x80000000)

/** Converts physical address to kernel address. */

#   define PA2KA(x)                 (((uintptr_t) (x)) + 0x80000000)

#ifndef __ASM__

#else

/** Converts kernel address to physical address. */

#   define KA2PA(x)                 ((x) - 0x80000000)

#   define KA2PA(x)         (((uintptr_t) (x)) - 0x80000000)

#   define PA2KA(x)                 ((x) + 0x80000000)

/** Converts physical address to kernel address. */

#endif

#   define PA2KA(x)         (((uintptr_t) (x)) + 0x80000000)

#else

#   define KA2PA(x)         ((x) - 0x80000000)

/** Number of entries in PTL0. */

#   define PA2KA(x)         ((x) + 0x80000000)

#define PTL0_ENTRIES                (1<<12)             /* 4096 */

#endif

/** Size of an entry in PTL0. */

#define PTL0_ENTRY_SIZE             4

/** Number of entries in PTL0. */

#define PTL0_ENTRIES            (1 << 12)   /* 4096 */

/** Returns number of frame the address belongs to. */

#define ADDR2PFN( addr )            ( ((uintptr_t)(addr)) >> FRAME_WIDTH )

/** Size of an entry in PTL0. */

#define PTL0_ENTRY_SIZE         4

/** Describes "section" page table entry (one-level paging with 1MB sized pages). */  

#define PTE_DESCRIPTOR_SECTION      0x2

/** Returns number of frame the address belongs to. */

#define ADDR2PFN(addr)          (((uintptr_t) (addr)) >> FRAME_WIDTH)

/** Page table access rights: user - no access, kernel - read/write. */

#define PTE_AP_USER_NO_KERNEL_RW    0x1

/** Describes "section" page table entry (one-level paging with 1MB sized pages). */  

#define PTE_DESCRIPTOR_SECTION      0x2

#ifndef __ASM__

/** Page table access rights: user - no access, kernel - read/write. */

#define PTE_AP_USER_NO_KERNEL_RW    0x1

/** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized

 * pages). Used only while booting the kernel.

#ifndef __ASM__

 */

typedef struct {

    unsigned descriptor_type     : 2;

/** Page table level 0 entry - "section" format is used (one-level paging, 1MB

    unsigned bufferable          : 1;

 * sized pages). Used only while booting the kernel.

    unsigned cacheable           : 1;

 */

    unsigned impl_specific       : 1;

typedef struct {

    unsigned domain              : 4;

    unsigned descriptor_type : 2;

    unsigned should_be_zero_1    : 1;

    unsigned bufferable : 1;

    unsigned access_permission   : 2;  

    unsigned cacheable : 1;

    unsigned should_be_zero_2    : 8;

    unsigned impl_specific : 1;

    unsigned section_base_addr   : 12;

    unsigned domain : 4;

} __attribute__ ((packed)) pte_level0_section_t;

    unsigned should_be_zero_1 : 1;

    unsigned access_permission : 2;    

    unsigned should_be_zero_2 : 8;

/** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */

    unsigned section_base_addr : 12;

extern pte_level0_section_t page_table[PTL0_ENTRIES];

} __attribute__ ((packed)) pte_level0_section_t;

extern void mmu_start(void);

/** Page table that holds 1:1 virtual to physical mapping used while booting the

 * kernel.

/** Enables paging. */

 */

static inline void enable_paging()

extern pte_level0_section_t page_table[PTL0_ENTRIES];

{

    /* c3 - each two bits controls access to the one of domains (16)

extern void mmu_start(void);

     *      0b01 - behave as a client (user) of a domain

     */

    asm volatile (

/** Enables paging. */

        // behave as a client of domains

static inline void enable_paging()

        "ldr r0, =0x55555555       \n"

{

        "mcr p15, 0, r0, c3, c0, 0 \n"

    /* c3 - each two bits controls access to the one of domains (16)

     *      0b01 - behave as a client (user) of a domain

        // current settings

     */

        "mrc p15, 0, r0, c1, c0, 0 \n"

    asm volatile (

        /* behave as a client of domains */

        // mask to enable paging

        "ldr r0, =0x55555555\n"

        "ldr r1, =0x00000001       \n"

        "mcr p15, 0, r0, c3, c0, 0\n"

        "orr r0, r0, r1            \n"

        /* current settings */

        // store settings

        "mrc p15, 0, r0, c1, c0, 0\n"

        "mcr p15, 0, r0, c1, c0, 0 \n"

        :

        /* mask to enable paging */

        :

        "ldr r1, =0x00000001\n"

        : "r0", "r1"

        "orr r0, r0, r1\n"

    );

}

        /* store settings */

        "mcr p15, 0, r0, c1, c0, 0\n"

        :

/** Sets the address of level 0 page table to CP15 register 2.

        :

 *

        : "r0", "r1"

 * @param pt Address of a page table to set.

    );

 */  

}

static inline void set_ptl0_address(pte_level0_section_t* pt)

{

    asm volatile (

/** Sets the address of level 0 page table to CP15 register 2.

        "mcr p15, 0, %0, c2, c0, 0 \n"

 *

        :

 * @param pt Address of a page table to set.

        : "r"(pt)

 */  

    );

static inline void set_ptl0_address(pte_level0_section_t* pt)

}

{

    asm volatile (

        "mcr p15, 0, %0, c2, c0, 0\n"

#endif

        :

        : "r" (pt)

#endif

    );

}

/** @}

 */

#endif