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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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- 
 
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/** IRQ notification framework
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 *
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 * This framework allows applications to register to receive a notification
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 * when interrupt is detected. The application may provide a simple 'top-half'
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 * handler as part of its registration, which can perform simple operations
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 * (read/write port/memory, add information to notification ipc message).
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 *
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 * The structure of a notification message is as follows:
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 * - METHOD: IPC_M_INTERRUPT
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 * - ARG1: interrupt number
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 * - ARG2: payload modified by a 'top-half' handler
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 * - ARG3: interrupt counter (may be needed to assure correct order
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 *         in multithreaded drivers)
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 */
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#include <arch.h>
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#include <arch.h>
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#include <mm/slab.h>
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#include <mm/slab.h>
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#include <errno.h>
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#include <errno.h>
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#include <ipc/ipc.h>
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#include <ipc/ipc.h>
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#include <ipc/irq.h>
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#include <ipc/irq.h>
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#include <atomic.h>
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typedef struct {
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typedef struct {
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    SPINLOCK_DECLARE(lock);
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    SPINLOCK_DECLARE(lock);
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    answerbox_t *box;
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    answerbox_t *box;
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    irq_code_t *code;
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    irq_code_t *code;
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    atomic_t counter;
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} ipc_irq_t;
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} ipc_irq_t;
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static ipc_irq_t *irq_conns = NULL;
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static ipc_irq_t *irq_conns = NULL;
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static int irq_conns_size;
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static int irq_conns_size;
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            *((__u32 *)code->cmds[i].addr) = code->cmds[i].value;
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            *((__u32 *)code->cmds[i].addr) = code->cmds[i].value;
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            break;
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            break;
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        case CMD_MEM_WRITE_8:
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        case CMD_MEM_WRITE_8:
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            *((__u64 *)code->cmds[i].addr) = code->cmds[i].value;
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            *((__u64 *)code->cmds[i].addr) = code->cmds[i].value;
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            break;
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            break;
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#if defined(ia32) || defined(amd64)
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        case CMD_PORT_READ_1:
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            IPC_SET_ARG2(call->data, inb((long)code->cmds[i].addr));
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            break;
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        case CMD_PORT_WRITE_1:
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            outb((long)code->cmds[i].addr, code->cmds[i].value);
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            break;
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#endif
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        default:
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        default:
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            break;
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            break;
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        }
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        }
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    }
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    }
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}
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}
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        code_free(code);
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        code_free(code);
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        return EEXISTS;
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        return EEXISTS;
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    }
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    }
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    irq_conns[irq].box = box;
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    irq_conns[irq].box = box;
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    irq_conns[irq].code = code;
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    irq_conns[irq].code = code;
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    atomic_set(&irq_conns[irq].counter, 0);
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    spinlock_unlock(&irq_conns[irq].lock);
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    spinlock_unlock(&irq_conns[irq].lock);
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    interrupts_restore(ipl);
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    interrupts_restore(ipl);
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    return 0;
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    return 0;
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}
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}
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    if (irq_conns[irq].box) {
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    if (irq_conns[irq].box) {
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        call = ipc_call_alloc(FRAME_ATOMIC);
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        call = ipc_call_alloc(FRAME_ATOMIC);
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        call->flags |= IPC_CALL_NOTIF;
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        call->flags |= IPC_CALL_NOTIF;
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        IPC_SET_METHOD(call->data, IPC_M_INTERRUPT);
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        IPC_SET_METHOD(call->data, IPC_M_INTERRUPT);
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        IPC_SET_ARG1(call->data, irq);
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        IPC_SET_ARG1(call->data, irq);
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        IPC_SET_ARG3(call->data, atomic_preinc(&irq_conns[irq].counter));
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        /* Execute code to handle irq */
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        /* Execute code to handle irq */
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        code_execute(call, irq_conns[irq].code);
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        code_execute(call, irq_conns[irq].code);
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 208 
 
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        spinlock_lock(&irq_conns[irq].box->irq_lock);
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        spinlock_lock(&irq_conns[irq].box->irq_lock);