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Line 107... | Line 107... | ||
107 | 107 | ||
108 | tlb_invalidate_all(); |
108 | tlb_invalidate_all(); |
109 | 109 | ||
110 | dmmu_enable(); |
110 | dmmu_enable(); |
111 | immu_enable(); |
111 | immu_enable(); |
112 | 112 | } |
|
113 | /* |
- | |
114 | * Quick hack: map frame buffer |
- | |
115 | */ |
- | |
116 | fr.address = FB_PHYS_ADDRESS; |
- | |
117 | pg.address = FB_VIRT_ADDRESS; |
- | |
118 | - | ||
119 | tag.value = ASID_KERNEL; |
- | |
120 | tag.vpn = pg.vpn; |
- | |
121 | - | ||
122 | dtlb_tag_access_write(tag.value); |
- | |
123 | 113 | ||
124 | data.value = 0; |
114 | /** Insert privileged mapping into DMMU TLB. |
125 | data.v = true; |
115 | * |
126 | data.size = PAGESIZE_4M; |
116 | * @param page Virtual page address. |
127 | data.pfn = fr.pfn; |
117 | * @param frame Physical frame address. |
128 | data.l = true; |
118 | * @param pagesize Page size. |
- | 119 | * @param locked True for permanent mappings, false otherwise. |
|
- | 120 | * @param cacheable True if the mapping is cacheable, false otherwise. |
|
129 | data.cp = 0; |
121 | */ |
- | 122 | void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable) |
|
- | 123 | { |
|
130 | data.cv = 0; |
124 | tlb_tag_access_reg_t tag; |
131 | data.p = true; |
125 | tlb_data_t data; |
132 | data.w = true; |
126 | page_address_t pg; |
133 | data.g = true; |
127 | frame_address_t fr; |
134 | 128 | ||
135 | dtlb_data_in_write(data.value); |
- | |
136 | - | ||
137 | /* |
- | |
138 | * Quick hack: map keyboard |
- | |
139 | */ |
- | |
140 | fr.address = KBD_PHYS_ADDRESS; |
129 | pg.address = page; |
141 | pg.address = KBD_VIRT_ADDRESS; |
130 | fr.address = frame; |
142 | 131 | ||
143 | tag.value = ASID_KERNEL; |
132 | tag.value = ASID_KERNEL; |
144 | tag.vpn = pg.vpn; |
133 | tag.vpn = pg.vpn; |
145 | 134 | ||
146 | dtlb_tag_access_write(tag.value); |
135 | dtlb_tag_access_write(tag.value); |
147 | 136 | ||
148 | data.value = 0; |
137 | data.value = 0; |
149 | data.v = true; |
138 | data.v = true; |
150 | data.size = PAGESIZE_8K; |
139 | data.size = pagesize; |
151 | data.pfn = fr.pfn; |
140 | data.pfn = fr.pfn; |
152 | data.l = true; |
141 | data.l = locked; |
153 | data.cp = 0; |
142 | data.cp = cacheable; |
154 | data.cv = 0; |
143 | data.cv = cacheable; |
155 | data.p = true; |
144 | data.p = true; |
156 | data.w = true; |
145 | data.w = true; |
157 | data.g = true; |
146 | data.g = true; |
158 | 147 | ||
159 | dtlb_data_in_write(data.value); |
148 | dtlb_data_in_write(data.value); |
Line 167... | Line 156... | ||
167 | 156 | ||
168 | /** DTLB miss handler. */ |
157 | /** DTLB miss handler. */ |
169 | void fast_data_access_mmu_miss(void) |
158 | void fast_data_access_mmu_miss(void) |
170 | { |
159 | { |
171 | tlb_tag_access_reg_t tag; |
160 | tlb_tag_access_reg_t tag; |
172 | tlb_data_t data; |
- | |
173 | __address tpc; |
161 | __address tpc; |
174 | char *tpc_str; |
162 | char *tpc_str; |
175 | 163 | ||
176 | tag.value = dtlb_tag_access_read(); |
164 | tag.value = dtlb_tag_access_read(); |
177 | if (tag.context != ASID_KERNEL || tag.vpn == 0) { |
165 | if (tag.context != ASID_KERNEL || tag.vpn == 0) { |
Line 184... | Line 172... | ||
184 | } |
172 | } |
185 | 173 | ||
186 | /* |
174 | /* |
187 | * Identity map piece of faulting kernel address space. |
175 | * Identity map piece of faulting kernel address space. |
188 | */ |
176 | */ |
189 | data.value = 0; |
- | |
190 | data.v = true; |
- | |
191 | data.size = PAGESIZE_8K; |
- | |
192 | data.pfn = tag.vpn; |
- | |
193 | data.l = false; |
- | |
194 | data.cp = 1; |
- | |
195 | data.cv = 1; |
- | |
196 | data.p = true; |
- | |
197 | data.w = true; |
- | |
198 | data.g = true; |
- | |
199 | - | ||
200 | dtlb_data_in_write(data.value); |
177 | dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true); |
201 | } |
178 | } |
202 | 179 | ||
203 | /** DTLB protection fault handler. */ |
180 | /** DTLB protection fault handler. */ |
204 | void fast_data_access_protection(void) |
181 | void fast_data_access_protection(void) |
205 | { |
182 | { |