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    struct {
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    struct {
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        unsigned long : 39; /**< Implementation dependent. */
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        unsigned long : 39; /**< Implementation dependent. */
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        unsigned nf : 1;    /**< Nonfaulting load. */
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        unsigned nf : 1;    /**< Nonfaulting load. */
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        unsigned asi : 8;   /**< ASI. */
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        unsigned asi : 8;   /**< ASI. */
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        unsigned tm : 1;    /**< TLB miss. */
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        unsigned tm : 1;    /**< TLB miss. */
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        unsigned : 3;
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        unsigned : 1;
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        unsigned ft : 5;    /**< Fault type. */
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        unsigned ft : 7;    /**< Fault type. */
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        unsigned e : 1;     /**< Side-effect bit. */
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        unsigned e : 1;     /**< Side-effect bit. */
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        unsigned ct : 2;    /**< Context Register selection. */
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        unsigned ct : 2;    /**< Context Register selection. */
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        unsigned pr : 1;    /**< Privilege bit. */
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        unsigned pr : 1;    /**< Privilege bit. */
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        unsigned w : 1;     /**< Write bit. */
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        unsigned w : 1;     /**< Write bit. */
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        unsigned ow : 1;    /**< Overwrite bit. */
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        unsigned ow : 1;    /**< Overwrite bit. */
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        unsigned fv : 1;    /**< Fayult Valid bit. */
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        unsigned fv : 1;    /**< Fault Valid bit. */
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    } __attribute__ ((packed));
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    } __attribute__ ((packed));
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};
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};
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typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
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typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
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/** Read MMU Primary Context Register.
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/** Read MMU Primary Context Register.
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{
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{
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    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
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    asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
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    flush();
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    flush();
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}
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}
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/** Read IMMU TLB Tag Access Register.
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 *
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 * @return Current value of IMMU TLB Tag Access Register.
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 */
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static inline __u64 itlb_tag_access_read(void)
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{
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    return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
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}
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/** Write DMMU TLB Tag Access Register.
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/** Write DMMU TLB Tag Access Register.
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 *
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 *
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 * @param v Value to be written.
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 * @param v Value to be written.
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 */
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 */
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static inline void dtlb_tag_access_write(__u64 v)
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static inline void dtlb_tag_access_write(__u64 v)
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{
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{
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    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
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    asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
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    flush();
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    flush();
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}
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}
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/** Read DMMU TLB Tag Access Register.
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 *
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 * @return Current value of DMMU TLB Tag Access Register.
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 */
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static inline __u64 dtlb_tag_access_read(void)
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{
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    return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
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}
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/** Write IMMU TLB Data in Register.
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/** Write IMMU TLB Data in Register.
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 *
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 *
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 * @param v Value to be written.
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 * @param v Value to be written.
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 */
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 */
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static inline void itlb_data_in_write(__u64 v)
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static inline void itlb_data_in_write(__u64 v)