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#define PAGESIZE_8K 0
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#define PAGESIZE_8K 0
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#define PAGESIZE_64K    1
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#define PAGESIZE_64K    1
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#define PAGESIZE_512K   2
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#define PAGESIZE_512K   2
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#define PAGESIZE_4M 3
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#define PAGESIZE_4M 3
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union tlb_context_reg {
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    __u64 v;
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    struct {
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        unsigned long : 51;
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        unsigned context : 13;      /**< Context/ASID. */
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    } __attribute__ ((packed));
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};
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typedef union tlb_context_reg tlb_context_reg_t;
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/** I-/D-TLB Data In/Access Register type. */
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/** I-/D-TLB Data In/Access Register type. */
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typedef tte_data_t tlb_data_t;
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typedef tte_data_t tlb_data_t;
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/** I-/D-TLB Data Access Address in Alternate Space. */
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/** I-/D-TLB Data Access Address in Alternate Space. */
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union tlb_data_access_addr {
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union tlb_data_access_addr {
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        unsigned : 4;       /**< Zero. */
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        unsigned : 4;       /**< Zero. */
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    } __attribute__ ((packed));
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    } __attribute__ ((packed));
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};
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};
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typedef union tlb_demap_addr tlb_demap_addr_t;
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typedef union tlb_demap_addr tlb_demap_addr_t;
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/** TLB Synchronous Fault Status Register. */
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union tlb_sfsr_reg {
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    __u64 value;
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    struct {
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        unsigned long : 39; /**< Implementation dependent. */
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        unsigned nf : 1;    /**< Nonfaulting load. */
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        unsigned asi : 8;   /**< ASI. */
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        unsigned tm : 1;    /**< TLB miss. */
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        unsigned : 3;
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        unsigned ft : 5;    /**< Fault type. */
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        unsigned e : 1;     /**< Side-effect bit. */
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        unsigned ct : 2;    /**< Context Register selection. */
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        unsigned pr : 1;    /**< Privilege bit. */
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        unsigned w : 1;     /**< Write bit. */
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        unsigned ow : 1;    /**< Overwrite bit. */
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        unsigned fv : 1;    /**< Fayult Valid bit. */
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    } __attribute__ ((packed));
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};
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typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
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/** Read MMU Primary Context Register.
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 *
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 * @return Current value of Primary Context Register.
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 */
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static inline __u64 mmu_primary_context_read(void)
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{
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    return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
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}
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/** Write MMU Primary Context Register.
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 *
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 * @param v New value of Primary Context Register.
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 */
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static inline void mmu_primary_context_write(__u64 v)
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{
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    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
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    flush();
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}
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/** Read MMU Secondary Context Register.
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 *
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 * @return Current value of Secondary Context Register.
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 */
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static inline __u64 mmu_secondary_context_read(void)
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{
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    return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
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}
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/** Write MMU Primary Context Register.
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 *
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 * @param v New value of Primary Context Register.
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 */
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static inline void mmu_secondary_context_write(__u64 v)
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{
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    asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
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    flush();
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}
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/** Read IMMU TLB Data Access Register.
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/** Read IMMU TLB Data Access Register.
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 *
 165 
 *
99 
 * @param entry TLB Entry index.
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 * @param entry TLB Entry index.
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 *
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 *
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 * @return Current value of specified IMMU TLB Data Access Register.
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 * @return Current value of specified IMMU TLB Data Access Register.
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{
 289 
{
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    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
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    asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
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    flush();
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    flush();
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}
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}
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/** Read ITLB Synchronous Fault Status Register.
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 *
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 * @return Current content of I-SFSR register.
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 297 
 */
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static inline __u64 itlb_sfsr_read(void)
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 299 
{
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    return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
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}
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/** Write ITLB Synchronous Fault Status Register.
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 *
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 * @param v New value of I-SFSR register.
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 306 
 */
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static inline void itlb_sfsr_write(__u64 v)
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{
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    asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
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    flush();
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}
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/** Read DTLB Synchronous Fault Status Register.
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 *
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 * @return Current content of D-SFSR register.
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 */
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static inline __u64 dtlb_sfsr_read(void)
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 318 
{
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    return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
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 320 
}
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 321 
 
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 322 
/** Write DTLB Synchronous Fault Status Register.
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 323 
 *
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 324 
 * @param v New value of D-SFSR register.
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 325 
 */
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 326 
static inline void dtlb_sfsr_write(__u64 v)
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 327 
{
- 
 
 328 
    asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
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 329 
    flush();
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 330 
}
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 331 
 
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 332 
/** Read DTLB Synchronous Fault Address Register.
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 333 
 *
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 334 
 * @return Current content of D-SFAR register.
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 335 
 */
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 336 
static inline __u64 dtlb_sfar_read(void)
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 337 
{
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 338 
    return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
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 339 
}
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 340 
 
227 
/** Perform IMMU TLB Demap Operation.
 341 
/** Perform IMMU TLB Demap Operation.
228 
 *
 342 
 *
229 
 * @param type Selects between context and page demap.
 343 
 * @param type Selects between context and page demap.
230 
 * @param context_encoding Specifies which Context register has Context ID for demap.
 344 
 * @param context_encoding Specifies which Context register has Context ID for demap.
231 
 * @param page Address which is on the page to be demapped.
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 * @param page Address which is on the page to be demapped.