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112 | /** Write IMMU TLB Data Access Register. |
112 | /** Write IMMU TLB Data Access Register. |
113 | * |
113 | * |
114 | * @param entry TLB Entry index. |
114 | * @param entry TLB Entry index. |
115 | * @param value Value to be written. |
115 | * @param value Value to be written. |
116 | */ |
116 | */ |
117 | static inline __u64 itlb_data_access_write(index_t entry, __u64 value) |
117 | static inline void itlb_data_access_write(index_t entry, __u64 value) |
118 | { |
118 | { |
119 | tlb_data_access_addr_t reg; |
119 | tlb_data_access_addr_t reg; |
120 | 120 | ||
121 | reg.value = 0; |
121 | reg.value = 0; |
122 | reg.tlb_entry = entry; |
122 | reg.tlb_entry = entry; |
Line 142... | Line 142... | ||
142 | /** Write DMMU TLB Data Access Register. |
142 | /** Write DMMU TLB Data Access Register. |
143 | * |
143 | * |
144 | * @param entry TLB Entry index. |
144 | * @param entry TLB Entry index. |
145 | * @param value Value to be written. |
145 | * @param value Value to be written. |
146 | */ |
146 | */ |
147 | static inline __u64 dtlb_data_access_write(index_t entry, __u64 value) |
147 | static inline void dtlb_data_access_write(index_t entry, __u64 value) |
148 | { |
148 | { |
149 | tlb_data_access_addr_t reg; |
149 | tlb_data_access_addr_t reg; |
150 | 150 | ||
151 | reg.value = 0; |
151 | reg.value = 0; |
152 | reg.tlb_entry = entry; |
152 | reg.tlb_entry = entry; |