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    lsu_cr_reg_t cr;
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    lsu_cr_reg_t cr;
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    cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
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    cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
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    cr.im = enable;
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    cr.im = enable;
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    asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
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    asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
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    flush();
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    membar();
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}
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}
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/** Disable or Enable DMMU. */
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/** Disable or Enable DMMU. */
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static inline void dmmu_set(bool enable)
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static inline void dmmu_set(bool enable)
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{
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{
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    lsu_cr_reg_t cr;
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    lsu_cr_reg_t cr;
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    cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
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    cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
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    cr.dm = enable;
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    cr.dm = enable;
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    asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
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    asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
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    flush();
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    membar();
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}
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}
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#endif
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#endif