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| Rev 619 | Rev 658 | ||
|---|---|---|---|
| Line 101... | Line 101... | ||
| 101 | #define immu_disable() immu_set(false) |
101 | #define immu_disable() immu_set(false) |
| 102 | #define dmmu_enable() dmmu_set(true) |
102 | #define dmmu_enable() dmmu_set(true) |
| 103 | #define dmmu_disable() dmmu_set(false) |
103 | #define dmmu_disable() dmmu_set(false) |
| 104 | 104 | ||
| 105 | /** Disable or Enable IMMU. */ |
105 | /** Disable or Enable IMMU. */ |
| 106 | static inline immu_set(bool enable) |
106 | static inline void immu_set(bool enable) |
| 107 | { |
107 | { |
| 108 | lsu_cr_reg_t cr; |
108 | lsu_cr_reg_t cr; |
| 109 | 109 | ||
| 110 | cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0); |
110 | cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0); |
| 111 | cr.im = enable; |
111 | cr.im = enable; |
| 112 | asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value); |
112 | asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value); |
| 113 | flush(); |
113 | flush(); |
| 114 | } |
114 | } |
| 115 | 115 | ||
| 116 | /** Disable or Enable DMMU. */ |
116 | /** Disable or Enable DMMU. */ |
| 117 | static inline dmmu_set(bool enable) |
117 | static inline void dmmu_set(bool enable) |
| 118 | { |
118 | { |
| 119 | lsu_cr_reg_t cr; |
119 | lsu_cr_reg_t cr; |
| 120 | 120 | ||
| 121 | cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0); |
121 | cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0); |
| 122 | cr.dm = enable; |
122 | cr.dm = enable; |