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| Rev 1220 | Rev 1267 | ||
|---|---|---|---|
| Line 38... | Line 38... | ||
| 38 | * value of EE. |
38 | * value of EE. |
| 39 | * |
39 | * |
| 40 | * @return Old interrupt priority level. |
40 | * @return Old interrupt priority level. |
| 41 | */ |
41 | */ |
| 42 | static inline ipl_t interrupts_enable(void) { |
42 | static inline ipl_t interrupts_enable(void) { |
| 43 | ipl_t v; |
43 | ipl_t v = 0; |
| 44 | ipl_t tmp; |
44 | ipl_t tmp; |
| 45 | 45 | ||
| 46 | __asm__ volatile ( |
46 | asm volatile ( |
| 47 | "mfmsr %0\n" |
47 | "mfmsr %0\n" |
| 48 | "mfmsr %1\n" |
48 | "mfmsr %1\n" |
| 49 | "ori %1, %1, 1 << 15\n" |
49 | "ori %1, %1, 1 << 15\n" |
| 50 | "mtmsr %1\n" |
50 | "mtmsr %1\n" |
| 51 | : "=r" (v), "=r" (tmp) |
51 | : "=r" (v), "=r" (tmp) |
| Line 62... | Line 62... | ||
| 62 | */ |
62 | */ |
| 63 | static inline ipl_t interrupts_disable(void) { |
63 | static inline ipl_t interrupts_disable(void) { |
| 64 | ipl_t v; |
64 | ipl_t v; |
| 65 | ipl_t tmp; |
65 | ipl_t tmp; |
| 66 | 66 | ||
| 67 | __asm__ volatile ( |
67 | asm volatile ( |
| 68 | "mfmsr %0\n" |
68 | "mfmsr %0\n" |
| 69 | "mfmsr %1\n" |
69 | "mfmsr %1\n" |
| 70 | "rlwinm %1, %1, 0, 17, 15\n" |
70 | "rlwinm %1, %1, 0, 17, 15\n" |
| 71 | "mtmsr %1\n" |
71 | "mtmsr %1\n" |
| 72 | : "=r" (v), "=r" (tmp) |
72 | : "=r" (v), "=r" (tmp) |
| Line 81... | Line 81... | ||
| 81 | * @param ipl Saved interrupt priority level. |
81 | * @param ipl Saved interrupt priority level. |
| 82 | */ |
82 | */ |
| 83 | static inline void interrupts_restore(ipl_t ipl) { |
83 | static inline void interrupts_restore(ipl_t ipl) { |
| 84 | ipl_t tmp; |
84 | ipl_t tmp; |
| 85 | 85 | ||
| 86 | __asm__ volatile ( |
86 | asm volatile ( |
| 87 | "mfmsr %1\n" |
87 | "mfmsr %1\n" |
| 88 | "rlwimi %0, %1, 0, 17, 15\n" |
88 | "rlwimi %0, %1, 0, 17, 15\n" |
| 89 | "cmpw 0, %0, %1\n" |
89 | "cmpw 0, %0, %1\n" |
| 90 | "beq 0f\n" |
90 | "beq 0f\n" |
| 91 | "mtmsr %0\n" |
91 | "mtmsr %0\n" |
| Line 101... | Line 101... | ||
| 101 | * |
101 | * |
| 102 | * @return Current interrupt priority level. |
102 | * @return Current interrupt priority level. |
| 103 | */ |
103 | */ |
| 104 | static inline ipl_t interrupts_read(void) { |
104 | static inline ipl_t interrupts_read(void) { |
| 105 | ipl_t v; |
105 | ipl_t v; |
| - | 106 | ||
| 106 | __asm__ volatile ( |
107 | asm volatile ( |
| 107 | "mfmsr %0\n" |
108 | "mfmsr %0\n" |
| 108 | : "=r" (v) |
109 | : "=r" (v) |
| 109 | ); |
110 | ); |
| 110 | return v; |
111 | return v; |
| 111 | } |
112 | } |
| Line 118... | Line 119... | ||
| 118 | */ |
119 | */ |
| 119 | static inline __address get_stack_base(void) |
120 | static inline __address get_stack_base(void) |
| 120 | { |
121 | { |
| 121 | __address v; |
122 | __address v; |
| 122 | 123 | ||
| - | 124 | asm volatile ( |
|
| - | 125 | "and %0, %%sp, %1\n" |
|
| - | 126 | : "=r" (v) |
|
| 123 | __asm__ volatile ("and %0, %%sp, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); |
127 | : "r" (~(STACK_SIZE - 1)) |
| 124 | 128 | ); |
|
| 125 | return v; |
129 | return v; |
| 126 | } |
130 | } |
| 127 | 131 | ||
| 128 | static inline void cpu_sleep(void) |
132 | static inline void cpu_sleep(void) |
| 129 | { |
133 | { |